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Searched refs:csrno (Results 1 – 6 of 6) sorted by relevance

/qemu/target/riscv/
H A Dcsr.c38 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) in riscv_get_csr_ops() argument
40 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)]; in riscv_get_csr_ops()
43 void riscv_set_csr_ops(int csrno, const riscv_csr_operations *ops) in riscv_set_csr_ops() argument
45 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops; in riscv_set_csr_ops()
82 static RISCVException fs(CPURISCVState *env, int csrno) in fs() argument
97 static RISCVException vs(CPURISCVState *env, int csrno) in vs() argument
110 static RISCVException ctr(CPURISCVState *env, int csrno) in ctr() argument
119 if (rv32 && csrno >= CSR_CYCLEH) { in ctr()
123 ctr_index = csrno - base_csrno; in ctr()
126 if ((csrno >= CSR_CYCLE && csrno <= CSR_INSTRET) || in ctr()
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H A Dcpu.h840 RISCVException riscv_csrr(CPURISCVState *env, int csrno,
843 RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
846 RISCVException riscv_csrrw_debug(CPURISCVState *env, int csrno,
851 static inline void riscv_csr_write(CPURISCVState *env, int csrno, in riscv_csr_write() argument
854 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS), 0); in riscv_csr_write()
857 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) in riscv_csr_read() argument
860 riscv_csrrw(env, csrno, &val, 0, 0, 0); in riscv_csr_read()
865 int csrno);
866 typedef RISCVException (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
868 typedef RISCVException (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
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H A Dth_csr.c30 static RISCVException smode(CPURISCVState *env, int csrno) in smode() argument
44 static RISCVException read_th_sxstatus(CPURISCVState *env, int csrno, in read_th_sxstatus() argument
54 .csrno = CSR_TH_SXSTATUS,
H A Dcpu.c482 int csrno = csr_list[i].csrno; in riscv_register_custom_csrs() local
485 riscv_set_csr_ops(csrno, csr_ops); in riscv_register_custom_csrs()
566 int csrno = dump_csrs[i]; in riscv_cpu_dump_state() local
568 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); in riscv_cpu_dump_state()
576 csr_ops[csrno].name, val); in riscv_cpu_dump_state()
615 int csrno = dump_rvv_csrs[i]; in riscv_cpu_dump_state() local
617 RISCVException res = riscv_csrrw_debug(env, csrno, &val, 0, 0); in riscv_cpu_dump_state()
625 csr_ops[csrno].name, val); in riscv_cpu_dump_state()
/qemu/hw/riscv/
H A Driscv_hart.c65 static void csr_call(char *cmd, uint64_t cpu_num, int csrno, uint64_t *val) in csr_call() argument
72 ret = riscv_csrr(env, csrno, (target_ulong *)val); in csr_call()
74 ret = riscv_csrrw(env, csrno, NULL, *(target_ulong *)val, in csr_call()
/qemu/disas/
H A Driscv.c2261 static const char *csr_name(int csrno) in csr_name() argument
2263 switch (csrno) { in csr_name()