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Searched refs:cq_mask (Results 1 – 2 of 2) sorted by relevance

/qemu/hw/riscv/
H A Driscv-iommu.h56 uint32_t cq_mask; /* Command queue index bit mask */ member
H A Driscv-iommu.c1644 tail = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_CQT) & s->cq_mask; in riscv_iommu_process_cq_tail()
1645 head = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_CQH) & s->cq_mask; in riscv_iommu_process_cq_tail()
1806 head = (head + 1) & s->cq_mask; in riscv_iommu_process_cq_tail()
1827 s->cq_mask = (2ULL << get_field(base, RISCV_IOMMU_CQB_LOG2SZ)) - 1; in riscv_iommu_process_cq_control()
1829 stl_le_p(&s->regs_ro[RISCV_IOMMU_REG_CQT], ~s->cq_mask); in riscv_iommu_process_cq_control()