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Searched refs:cpu_regs (Results 1 – 5 of 5) sorted by relevance

/qemu/target/rx/
H A Dtranslate.c66 static TCGv cpu_regs[16]; variable
73 #define cpu_sp cpu_regs[0]
185 tcg_gen_shli_i32(mem, cpu_regs[ri], size); in rx_gen_regindex()
186 tcg_gen_add_i32(mem, mem, cpu_regs[rb]); in rx_gen_regindex()
197 return cpu_regs[reg]; in rx_index_addr()
200 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); in rx_index_addr()
205 tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); in rx_index_addr()
232 return cpu_regs[rs]; in rx_load_source()
434 tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); in trans_MOV_rm()
435 rx_gen_st(a->sz, cpu_regs[a->rs], mem); in trans_MOV_rm()
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/qemu/target/i386/tcg/
H A Dtranslate.c80 static TCGv cpu_regs[CPU_NB_REGS]; variable
448 dest = dest ? dest : cpu_regs[reg - 4]; in gen_op_deposit_reg_v()
449 tcg_gen_deposit_tl(dest, cpu_regs[reg - 4], t0, 8, 8); in gen_op_deposit_reg_v()
450 return cpu_regs[reg - 4]; in gen_op_deposit_reg_v()
452 dest = dest ? dest : cpu_regs[reg]; in gen_op_deposit_reg_v()
453 tcg_gen_deposit_tl(dest, cpu_regs[reg], t0, 0, 8); in gen_op_deposit_reg_v()
456 dest = dest ? dest : cpu_regs[reg]; in gen_op_deposit_reg_v()
457 tcg_gen_deposit_tl(dest, cpu_regs[reg], t0, 0, 16); in gen_op_deposit_reg_v()
462 dest = dest ? dest : cpu_regs[reg]; in gen_op_deposit_reg_v()
467 dest = dest ? dest : cpu_regs[reg]; in gen_op_deposit_reg_v()
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H A Demit.c.inc81 tcg_gen_sextract_tl(ofs, cpu_regs[opn], 3, poslen - 3);
280 tcg_gen_sextract_tl(v, cpu_regs[op->n - 4], 8, 8);
282 tcg_gen_extract_tl(v, cpu_regs[op->n - 4], 8, 8);
286 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot | MO_SIGN);
288 tcg_gen_ext_tl(v, cpu_regs[op->n], op->ot);
1683 * cmpv will be moved to cc_src *after* cpu_regs[] is written back, so use
1686 tcg_gen_ext_tl(cmpv, cpu_regs[decode->op[1].n], ot_full);
1760 tcg_gen_ext_tl(cmpv, cpu_regs[R_EAX], ot);
1783 * directly on cpu_regs. In case rm is part of RAX, note that this
1812 tcg_gen_concat_i64_i128(cmp, cpu_regs[R_EAX], cpu_regs[R_EDX]);
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/qemu/target/openrisc/
H A Dtranslate.c75 static TCGv cpu_regs[32]; variable
128 cpu_regs[i] = tcg_global_mem_new(tcg_env, in openrisc_translate_init()
167 return cpu_regs[reg]; in cpu_R()
178 dc->R0 = cpu_regs[0]; in check_r0_write()
596 tcg_gen_movi_tl(cpu_regs[9], ret_pc); in trans_l_jal()
638 tcg_gen_movi_tl(cpu_regs[9], dc->base.pc_next + 8); in trans_l_jalr()
1551 dc->R0 = cpu_regs[0]; in openrisc_tr_tb_start()
/qemu/target/sparc/
H A Dtranslate.c111 static TCGv cpu_regs[32]; variable
334 return cpu_regs[reg]; in gen_load_gpr()
346 tcg_gen_mov_tl(cpu_regs[reg], v); in gen_store_gpr()
354 return cpu_regs[reg]; in gen_dest_gpr()
3722 func(dst, src1, cpu_regs[a->rs2_or_imm]); in do_arith_int()
3794 gen_store_gpr(dc, a->rd, cpu_regs[a->rs2_or_imm]); in TRANS()
3829 tcg_gen_trunc_tl_i32(n2, cpu_regs[a->rs2_or_imm]); in trans_UDIV()
3836 tcg_gen_ext32u_i64(t2, cpu_regs[a->rs2_or_imm]); in trans_UDIV()
3838 tcg_gen_extu_i32_i64(t2, cpu_regs[a->rs2_or_imm]); in trans_UDIV()
3880 src2 = cpu_regs[a->rs2_or_imm]; in trans_UDIVX()
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