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Searched refs:clr (Results 1 – 6 of 6) sorted by relevance

/qemu/hw/riscv/
H A Driscv-iommu.h120 unsigned idx, uint32_t set, uint32_t clr) in riscv_iommu_reg_mod32() argument
123 stl_le_p(s->regs_rw + idx, (val & ~clr) | set); in riscv_iommu_reg_mod32()
139 uint64_t set, uint64_t clr) in riscv_iommu_reg_mod64() argument
142 stq_le_p(s->regs_rw + idx, (val & ~clr) | set); in riscv_iommu_reg_mod64()
/qemu/tests/tcg/s390x/
H A Dper.S54 clr %r1, %r2 /* d3 != 0 */
62 clr %r1, %r2 /* d4 != 0 */
/qemu/target/rx/
H A Ddisas.c1241 BOP_IM(clr, a->rs); in trans_BCLR_im()
1247 BOP_RM(clr); in trans_BCLR_rm()
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc1141 TCGv_i64 tmp, set, clr;
1145 clr = tcg_temp_new_i64();
1150 tcg_gen_or_i64(clr, set, tmp);
1153 tcg_gen_setcondi_i64(TCG_COND_EQ, clr, clr, 0);
1154 tcg_gen_shli_i64(clr, clr, 1);
1159 tcg_gen_or_i64(tmp, set, clr);
/qemu/hw/nvme/
H A Dtrace-events95 pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrupt mask clr, data=0x%"…
/qemu/target/m68k/
H A Dtranslate.c2578 DISAS_INSN(clr) in DISAS_INSN() argument
5827 BASE(clr, 4200, ff00); in register_m68k_insns()