| /qemu/docs/ |
| H A D | bypass-iommu.txt | 8 is not flexible. We introduce this bypass iommu property to support
14 determine whether the devices attached on the PCI host bridge will bypass
17 bypass vIOMMU. When bypass_iommu property is not set for a host bridge,
22 The bypass iommu feature support PXB host bridge and default main host
26 on AArch64. Other machine types do not support bypass iommu for default
29 1. The following is the bypass iommu options:
34 (3) X86 default root bus bypass iommu:
46 - a default host bridge which bypass SMMUv3
48 - a pxb host bridge which bypass SMMUv3
60 - a default host bridge which bypass iommu
[all …]
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| /qemu/hw/virtio/ |
| H A D | virtio-iommu.c | 50 bool bypass; member
94 bypassed = s->config.bypass; in virtio_iommu_device_bypassed()
100 bypassed = s->config.bypass; in virtio_iommu_device_bypassed()
102 bypassed = ep->domain->bypass; in virtio_iommu_device_bypassed()
355 bool bypass) in virtio_iommu_get_domain() argument
361 if (domain->bypass != bypass) { in virtio_iommu_get_domain()
371 domain->bypass = bypass; in virtio_iommu_get_domain()
816 if (domain->bypass) { in virtio_iommu_map()
866 if (domain->bypass) { in virtio_iommu_unmap()
1166 bypass_allowed = s->config.bypass; in virtio_iommu_translate()
[all …]
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| H A D | trace-events | 115 …bypass) "page_size_mask=0x%"PRIx64" input range start=0x%"PRIx64" input range end=0x%"PRIx64" doma…
116 virtio_iommu_set_config(uint8_t bypass) "bypass=0x%x"
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| /qemu/tests/qapi-schema/ |
| H A D | type-bypass-bad-gen.err | 1 type-bypass-bad-gen.json: In command 'foo':
2 type-bypass-bad-gen.json:2: flag 'gen' may only use false value
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| H A D | meson.build | 180 'type-bypass-bad-gen.json',
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| /qemu/hw/block/ |
| H A D | pflash_cfi02.c | 82 int bypass; member
249 if (pfl->bypass) { in pflash_timer()
516 if (!pfl->bypass && boff != pfl->unlock_addr0) { in pflash_write()
522 pfl->bypass = 1; in pflash_write()
544 if (pfl->bypass) { in pflash_write()
567 if (pfl->bypass) in pflash_write()
571 if (pfl->bypass && cmd == 0x00) { in pflash_write()
700 pfl->bypass = 0; in pflash_write()
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| /qemu/hw/ppc/ |
| H A D | spapr_vio.c | 318 void spapr_vio_set_bypass(SpaprVioDevice *dev, bool bypass) in spapr_vio_set_bypass() argument
324 memory_region_set_enabled(&dev->mrbypass, bypass); in spapr_vio_set_bypass()
325 memory_region_set_enabled(spapr_tce_get_iommu(dev->tcet), !bypass); in spapr_vio_set_bypass()
327 dev->tcet->bypass = bypass; in spapr_vio_set_bypass()
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| H A D | spapr_iommu.c | 235 spapr_vio_set_bypass(tcet->vdev, tcet->bypass); in spapr_tce_table_post_load()
292 VMSTATE_BOOL(bypass, SpaprTceTable),
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| /qemu/include/standard-headers/linux/ |
| H A D | virtio_iommu.h | 40 uint8_t bypass; member
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| /qemu/tests/qtest/ |
| H A D | virtio-iommu-test.c | 34 uint8_t bypass = qvirtio_config_readb(dev, 36); in pci_config() local
40 g_assert_cmpint(bypass, ==, 1); in pci_config()
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| /qemu/include/hw/ppc/ |
| H A D | spapr_vio.h | 151 void spapr_vio_set_bypass(SpaprVioDevice *dev, bool bypass);
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| H A D | spapr.h | 878 bool bypass; member
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| /qemu/hw/arm/ |
| H A D | trace-events | 47 …(const char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x bypass (smmu disabled) io…
48 …st char *n, uint16_t sid, uint64_t addr, bool is_write) "%s sid=0x%x STE bypass iova:0x%"PRIx64" i…
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| /qemu/docs/system/devices/ |
| H A D | virtio-pmem.rst | 13 Virtio pmem allows to bypass the guest page cache and directly use
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| /qemu/docs/system/arm/ |
| H A D | virt.rst | 180 default-bus-bypass-iommu
182 <https://gitlab.com/qemu-project/qemu/-/blob/master/docs/bypass-iommu.txt>`_
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| /qemu/docs/devel/testing/ |
| H A D | acpi-bits.rst | 18 operating system (the OS). Operating systems tend to bypass bios problems and
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| /qemu/docs/system/riscv/ |
| H A D | sifive_u.rst | 333 This changes U-Boot to use the QEMU generated device tree blob, and bypass
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| /qemu/hw/net/ |
| H A D | trace-events | 136 …check, bool speed_select_bypass) "Set extended link params: ASD check: %d, Speed select bypass: %d"
280 …ass, bool pfrstd) "Set extended link params: ASD check: %d, Speed select bypass: %d, PF reset done…
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| /qemu/target/s390x/ |
| H A D | cpu_features_def.h.inc | 148 DEF_FEAT(SIE_IB, "ib", SCLP_CPU, 42, "SIE: Intervention bypass facility")
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| /qemu/docs/tools/ |
| H A D | qemu-img.rst | 914 that bypass the qcow2 metadata may corrupt the qcow2 metadata because the
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| /qemu/qapi/ |
| H A D | block-core.json | 3210 # @direct: enables use of O_DIRECT (bypass the host page cache;
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