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Searched refs:bar0 (Results 1 – 12 of 12) sorted by relevance

/qemu/tests/qtest/
H A Dac97-test.c54 QPCIBar bar0; in ac97_playback_upsample() local
57 bar0 = qpci_iomap(dev, 0, NULL); in ac97_playback_upsample()
59 qpci_io_writew(dev, bar0, 0x2c, 0x1); in ac97_playback_upsample()
70 QPCIBar bar0; in ac97_record_downsample() local
73 bar0 = qpci_iomap(dev, 0, NULL); in ac97_record_downsample()
75 qpci_io_writew(dev, bar0, 0x32, 0x1); in ac97_record_downsample()
H A Dvirtio-blk-test.c733 QPCIBar bar0; in test_nonexistent_virtqueue() local
740 bar0 = qpci_iomap(dev, 0, NULL); in test_nonexistent_virtqueue()
742 qpci_io_writeb(dev, bar0, VIRTIO_PCI_QUEUE_SEL, 2); in test_nonexistent_virtqueue()
743 qpci_io_writel(dev, bar0, VIRTIO_PCI_QUEUE_PFN, 1); in test_nonexistent_virtqueue()
H A Dvhost-user-blk-test.c776 QPCIBar bar0; in test_nonexistent_virtqueue() local
783 bar0 = qpci_iomap(dev, 0, NULL); in test_nonexistent_virtqueue()
785 qpci_io_writeb(dev, bar0, VIRTIO_PCI_QUEUE_SEL, 2); in test_nonexistent_virtqueue()
786 qpci_io_writel(dev, bar0, VIRTIO_PCI_QUEUE_PFN, 1); in test_nonexistent_virtqueue()
/qemu/hw/riscv/
H A Driscv-iommu-pci.c67 MemoryRegion bar0; /* PCI BAR (including MSI-x config) */ member
105 memory_region_init(&s->bar0, OBJECT(s), "riscv-iommu-bar0", in riscv_iommu_pci_realize()
107 memory_region_add_subregion(&s->bar0, 0, &iommu->regs_mr); in riscv_iommu_pci_realize()
112 PCI_BASE_ADDRESS_MEM_TYPE_64, &s->bar0); in riscv_iommu_pci_realize()
115 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG, in riscv_iommu_pci_realize()
116 &s->bar0, 0, RISCV_IOMMU_REG_MSI_CONFIG + 256, 0, &err); in riscv_iommu_pci_realize()
/qemu/hw/acpi/
H A Derst.c240 pcibus_t bar0 = pci_get_bar_addr(PCI_DEVICE(erst_dev), 0); in build_erst() local
245 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
251 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
257 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
263 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
269 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
275 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
281 .table_data = table_instruction_data, .bar = bar0, .flags = 0, in build_erst()
287 trace_acpi_erst_pci_bar_0(bar0); in build_erst()
/qemu/qapi/
H A Dcommon.json80 # @bar0: PCI BAR0 is used for the feature
95 'data': [ 'off', 'auto', 'bar0', 'bar1', 'bar2', 'bar3', 'bar4', 'bar5' ] }
/qemu/hw/pci-host/
H A Dppce500.c123 MemoryRegion bar0; member
424 memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space, in e500_pcihost_bridge_realize()
426 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); in e500_pcihost_bridge_realize()
/qemu/hw/net/
H A Dvmxnet3_defs.h68 MemoryRegion bar0; member
H A Dvmxnet3.c2193 memory_region_init_io(&s->bar0, OBJECT(s), &b0_ops, s, in vmxnet3_pci_realize()
2196 PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); in vmxnet3_pci_realize()
/qemu/hw/sparc64/
H A Dsun4u.c92 MemoryRegion bar0; member
363 memory_region_init_io(&s->bar0, OBJECT(s), &unassigned_io_ops, s, in ebus_realize()
365 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); in ebus_realize()
/qemu/hw/nvme/
H A Dnvme.h564 MemoryRegion bar0; member
H A Dctrl.c565 lo = n->bar0.addr; in nvme_addr_is_iomem()
566 hi = lo + int128_get64(n->bar0.size); in nvme_addr_is_iomem()
8697 memory_region_init(&n->bar0, OBJECT(n), "nvme-bar0", bar_size); in nvme_init_pci()
8700 memory_region_add_subregion(&n->bar0, 0, &n->iomem); in nvme_init_pci()
8703 pcie_sriov_vf_register_bar(pci_dev, 0, &n->bar0); in nvme_init_pci()
8706 PCI_BASE_ADDRESS_MEM_TYPE_64, &n->bar0); in nvme_init_pci()
8710 &n->bar0, 0, msix_table_offset, in nvme_init_pci()
8711 &n->bar0, 0, msix_pba_offset, 0, errp); in nvme_init_pci()
9046 msix_uninit(pci_dev, &n->bar0, &n->bar0); in nvme_exit()
9049 memory_region_del_subregion(&n->bar0, &n->iomem); in nvme_exit()