| /qemu/hw/misc/ |
| H A D | stm32l4x5_exti.c | 69 static unsigned valid_mask(unsigned bank) in valid_mask() argument
71 return MAKE_64BIT_MASK(0, irqs_per_bank[bank]); in valid_mask()
74 static unsigned configurable_mask(unsigned bank) in configurable_mask() argument
76 return valid_mask(bank) & ~exti_romask[bank]; in configurable_mask()
83 for (unsigned bank = 0; bank < EXTI_NUM_REGISTER; bank++) { in stm32l4x5_exti_reset_hold() local
84 s->imr[bank] = exti_romask[bank]; in stm32l4x5_exti_reset_hold()
85 s->emr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
86 s->rtsr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
87 s->ftsr[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
88 s->swier[bank] = 0x00000000; in stm32l4x5_exti_reset_hold()
[all …]
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| /qemu/hw/intc/ |
| H A D | omap_intc.c | 58 struct omap_intr_handler_bank_s bank[3]; member
73 level = s->bank[j].irqs & ~s->bank[j].mask & in omap_inth_sir_update()
74 (is_fiq ? s->bank[j].fiq : ~s->bank[j].fiq); in omap_inth_sir_update()
78 p = s->bank[j].priority[i]; in omap_inth_sir_update()
95 has_intr |= s->bank[i].irqs & ~s->bank[i].mask & in omap_inth_update()
96 (is_fiq ? s->bank[i].fiq : ~s->bank[i].fiq); in omap_inth_update()
113 struct omap_intr_handler_bank_s *bank = &ih->bank[irq >> 5]; in omap_set_intr() local
117 rise = ~bank->irqs & (1 << n); in omap_set_intr()
118 if (~bank->sens_edge & (1 << n)) in omap_set_intr()
119 rise &= ~bank->inputs; in omap_set_intr()
[all …]
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| H A D | armv7m_nvic.c | 229 int i, bank; in nvic_recompute_state_secure() local
246 for (bank = M_REG_S; bank >= M_REG_NS; bank--) { in nvic_recompute_state_secure()
251 if (bank == M_REG_S) { in nvic_recompute_state_secure()
270 pending_is_s_banked = (bank == M_REG_S); in nvic_recompute_state_secure()
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| H A D | arm_gicv3_cpuif.c | 2169 int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; in icc_ctlr_el1_read() local
2176 value = cs->icc_ctlr_el1[bank]; in icc_ctlr_el1_read()
2185 int bank = gicv3_use_ns_bank(env) ? GICV3_NS : GICV3_S; in icc_ctlr_el1_write() local
2207 cs->icc_ctlr_el1[bank] &= ~mask; in icc_ctlr_el1_write()
2208 cs->icc_ctlr_el1[bank] |= (value & mask); in icc_ctlr_el1_write()
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| /qemu/hw/ppc/ |
| H A D | ppc4xx_sdram.c | 111 static void sdram_bank_map(Ppc4xxSdramBank *bank) in sdram_bank_map() argument
113 trace_ppc4xx_sdram_map(bank->base, bank->size); in sdram_bank_map()
114 memory_region_init(&bank->container, NULL, "sdram-container", bank->size); in sdram_bank_map()
115 memory_region_add_subregion(&bank->container, 0, &bank->ram); in sdram_bank_map()
116 memory_region_add_subregion(get_system_memory(), bank->base, in sdram_bank_map()
117 &bank->container); in sdram_bank_map()
120 static void sdram_bank_unmap(Ppc4xxSdramBank *bank) in sdram_bank_unmap() argument
122 trace_ppc4xx_sdram_unmap(bank->base, bank->size); in sdram_bank_unmap()
123 memory_region_del_subregion(get_system_memory(), &bank->container); in sdram_bank_unmap()
124 memory_region_del_subregion(&bank->container, &bank->ram); in sdram_bank_unmap()
[all …]
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| H A D | ppc440_uc.c | 72 MemoryRegion bank[4]; member
174 memory_region_init_ram(&l2sram->bank[0], NULL, "ppc4xx.l2sram_bank0", in ppc4xx_l2sram_init()
176 memory_region_init_ram(&l2sram->bank[1], NULL, "ppc4xx.l2sram_bank1", in ppc4xx_l2sram_init()
178 memory_region_init_ram(&l2sram->bank[2], NULL, "ppc4xx.l2sram_bank2", in ppc4xx_l2sram_init()
180 memory_region_init_ram(&l2sram->bank[3], NULL, "ppc4xx.l2sram_bank3", in ppc4xx_l2sram_init()
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| /qemu/hw/net/ |
| H A D | smc91c111.c | 50 int bank; member
80 VMSTATE_INT32(bank, smc91c111_state),
362 s->bank = 0; in smc91c111_reset()
433 s->bank = value; in smc91c111_writeb()
438 switch (s->bank) { in smc91c111_writeb()
609 s->bank, offset, value); in smc91c111_writeb()
618 return s->bank; in smc91c111_readb()
622 switch (s->bank) { in smc91c111_readb()
756 s->bank, offset); in smc91c111_readb()
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| /qemu/tests/qtest/ |
| H A D | dm163-test.c | 115 const unsigned bank = (uintptr_t) opaque; in test_dm163_bank() local
116 const int width = bank ? 192 : 144; in test_dm163_bank()
123 GPIO_OUT(SELBK, bank); in test_dm163_bank()
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| H A D | npcm7xx_smbus-test.c | 161 static void choose_bank(QTestState *qts, uint64_t base_addr, uint8_t bank) in choose_bank() argument
165 if (bank) { in choose_bank()
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| /qemu/target/i386/ |
| H A D | helper.c | 367 int bank; member
389 uint64_t *banks = cenv->mce_banks + 4 * params->bank; in do_inject_x86_mce()
427 cs->cpu_index, params->bank); in do_inject_x86_mce()
473 void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, in cpu_x86_inject_mce() argument
481 .bank = bank, in cpu_x86_inject_mce()
494 if (bank >= bank_num) { in cpu_x86_inject_mce()
512 params.bank = 1; in cpu_x86_inject_mce()
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| H A D | monitor.c | 582 int bank = qdict_get_int(qdict, "bank"); in hmp_mce() local
595 cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc, in hmp_mce()
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| /qemu/include/hw/ppc/ |
| H A D | ppc4xx.h | 119 Ppc4xxSdramBank bank[4]; member
145 Ppc4xxSdramBank bank[4]; member
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| /qemu/target/sh4/ |
| H A D | op_helper.c | 456 int bank, i; in helper_fipr() local
459 bank = (env->sr & FPSCR_FR) ? 16 : 0; in helper_fipr()
464 p = float32_mul(env->fregs[bank + m + i], in helper_fipr()
465 env->fregs[bank + n + i], in helper_fipr()
471 env->fregs[bank + n + 3] = r; in helper_fipr()
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| /qemu/hw/mem/ |
| H A D | cxl_type3_stubs.c | 33 bool has_bank, uint8_t bank, in qmp_cxl_inject_dram_event() argument
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| H A D | cxl_type3.c | 1715 bool has_bank, uint8_t bank, in qmp_cxl_inject_dram_event() argument
1778 dram.bank = bank; in qmp_cxl_inject_dram_event()
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| /qemu/hw/i2c/ |
| H A D | npcm7xx_smbus.c | 660 uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; in npcm7xx_smbus_read() local
710 if (bank) { in npcm7xx_smbus_read()
821 uint8_t bank = s->ctl3 & NPCM7XX_SMBCTL3_BNK_SEL; in npcm7xx_smbus_write() local
877 if (bank) { in npcm7xx_smbus_write()
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| /qemu/include/hw/cxl/ |
| H A D | cxl_events.h | 143 uint8_t bank; member
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| /qemu/qapi/ |
| H A D | cxl.json | 119 # @bank-group: Bank group of the memory event location, incorporating
122 # @bank: Bank of the memory event location. A single bank is accessed
139 '*bank-group': 'uint8', '*bank': 'uint8', '*row': 'uint32',
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| /qemu/hw/display/ |
| H A D | cirrus_vga.c | 2437 static void map_linear_vram_bank(CirrusVGAState *s, unsigned bank) in map_linear_vram_bank() argument
2439 MemoryRegion *mr = &s->cirrus_bank[bank]; in map_linear_vram_bank()
2446 memory_region_set_alias_offset(mr, s->cirrus_bank_base[bank]); in map_linear_vram_bank()
2889 MemoryRegion *bank = &s->cirrus_bank[i]; in cirrus_init_common() local
2890 memory_region_init_alias(bank, owner, names[i], &s->vga.vram, in cirrus_init_common()
2892 memory_region_set_enabled(bank, false); in cirrus_init_common()
2894 bank, 1); in cirrus_init_common()
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| /qemu/docs/system/arm/ |
| H A D | vexpress.rst | 63 the first flash bank
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| /qemu/hw/smbios/ |
| H A D | smbios.c | 109 const char *loc_pfx, *bank, *manufacturer, *serial, *asset, *part; member
890 SMBIOS_TABLE_SET_STR(17, bank_locator_str, type17.bank); in smbios_build_type_17_table()
1531 save_opt(&type17.bank, opts, "bank"); in smbios_entry_add()
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| /qemu/pc-bios/dtb/ |
| H A D | canyonlands.dts | 229 bank-width = <2>;
272 bank-settings = <0x80002222>;
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| H A D | petalogix-s3adsp1800.dts | 131 bank-width = <0x01>;
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| H A D | petalogix-ml605.dts | 246 bank-width = < 0x02 >;
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| /qemu/linux-headers/asm-x86/ |
| H A D | kvm.h | 545 __u8 bank; member
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