/qemu/tests/tcg/loongarch64/system/ |
H A D | boot.S | 41 andi t0, t0, 0x20
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/qemu/target/microblaze/ |
H A D | insns.decode | 77 andi 101001 ..... ..... ................ @typeb
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H A D | translate.c | 326 DO_TYPEBI(andi, false, tcg_gen_andi_i32) in DO_TYPEA()
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/qemu/target/riscv/ |
H A D | insn16.decode | 154 andi 100 . 10 ... ..... 01 @c_andi
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H A D | insn32.decode | 155 andi ............ ..... 111 ..... 0010011 @i
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/qemu/target/openrisc/ |
H A D | disas.c | 106 INSN(andi, "r%d, r%d, %d", a->d, a->a, a->k)
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/qemu/target/loongarch/tcg/insn_trans/ |
H A D | trans_arith.c.inc | 302 TRANS(andi, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl)
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/qemu/disas/ |
H A D | microblaze.c | 107 bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, enumerator 366 …NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst },
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/qemu/target/s390x/tcg/ |
H A D | insn-data.h.inc | 100 D(0xc00a, NIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2020) 101 D(0xc00b, NILF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2000) 102 D(0xa504, NIHH, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1030) 103 D(0xa505, NIHL, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1020) 104 D(0xa506, NILH, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1010) 105 D(0xa507, NILL, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1000)
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H A D | translate_vx.c.inc | 3206 gen_gvec_fn_2i(andi, ES_32, v1, v2, (1ull << 31) - 1); 3225 gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1);
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/qemu/tcg/loongarch64/ |
H A D | tcg-target.c.inc | 1111 * bstrpick or andi is faster, so use bstrpick as it's not 2664 /* Canonical nop is andi r0,r0,0 */
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H A D | tcg-insn-defs.c.inc | 1819 /* Emits the `andi d, j, uk12` instruction. */
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/qemu/target/loongarch/ |
H A D | insns.decode | 151 andi 0000 001101 ............ ..... ..... @rr_ui12
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H A D | disas.c | 528 INSN(andi, rr_i) in INSN()
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/qemu/tcg/riscv/ |
H A D | tcg-target.c.inc | 1768 /* We are expecting alignment max 7, so we can always use andi. */
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/qemu/target/riscv/insn_trans/ |
H A D | trans_rvv.c.inc | 2110 GEN_OPIVI_GVEC_TRANS(vand_vi, IMM_SX, vand_vx, andi)
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