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Searched refs:andi (Results 1 – 16 of 16) sorted by relevance

/qemu/tests/tcg/loongarch64/system/
H A Dboot.S41 andi t0, t0, 0x20
/qemu/target/microblaze/
H A Dinsns.decode77 andi 101001 ..... ..... ................ @typeb
H A Dtranslate.c326 DO_TYPEBI(andi, false, tcg_gen_andi_i32) in DO_TYPEA()
/qemu/target/riscv/
H A Dinsn16.decode154 andi 100 . 10 ... ..... 01 @c_andi
H A Dinsn32.decode155 andi ............ ..... 111 ..... 0010011 @i
/qemu/target/openrisc/
H A Ddisas.c106 INSN(andi, "r%d, r%d, %d", a->d, a->a, a->k)
/qemu/target/loongarch/tcg/insn_trans/
H A Dtrans_arith.c.inc302 TRANS(andi, ALL, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl)
/qemu/disas/
H A Dmicroblaze.c107 bltd, ble, bled, bgt, bgtd, bge, bged, ori, andi, xori, andni, enumerator
366 …NO_OFFSET, NO_DELAY_SLOT, IMMVAL_MASK_NON_SPECIAL, 0xA4000000, OPCODE_MASK_H, andi, logical_inst },
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc100 D(0xc00a, NIHF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2020)
101 D(0xc00b, NILF, RIL_a, EI, r1_o, i2_32u, r1, 0, andi, 0, 0x2000)
102 D(0xa504, NIHH, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1030)
103 D(0xa505, NIHL, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1020)
104 D(0xa506, NILH, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1010)
105 D(0xa507, NILL, RI_a, Z, r1_o, i2_16u, r1, 0, andi, 0, 0x1000)
H A Dtranslate_vx.c.inc3206 gen_gvec_fn_2i(andi, ES_32, v1, v2, (1ull << 31) - 1);
3225 gen_gvec_fn_2i(andi, ES_64, v1, v2, (1ull << 63) - 1);
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc1111 * bstrpick or andi is faster, so use bstrpick as it's not
2664 /* Canonical nop is andi r0,r0,0 */
H A Dtcg-insn-defs.c.inc1819 /* Emits the `andi d, j, uk12` instruction. */
/qemu/target/loongarch/
H A Dinsns.decode151 andi 0000 001101 ............ ..... ..... @rr_ui12
H A Ddisas.c528 INSN(andi, rr_i) in INSN()
/qemu/tcg/riscv/
H A Dtcg-target.c.inc1768 /* We are expecting alignment max 7, so we can always use andi. */
/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc2110 GEN_OPIVI_GVEC_TRANS(vand_vi, IMM_SX, vand_vx, andi)