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Searched refs:am (Results 1 – 9 of 9) sorted by relevance

/qemu/target/mips/system/
H A Dphysaddr.c24 static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) in is_seg_am_mapped() argument
64 if ((adetlb_mask << am) < 0) { in is_seg_am_mapped()
71 return ((adetlb_mask << am) < 0); in is_seg_am_mapped()
80 unsigned int am, bool eu, in get_seg_physical_address() argument
84 int mapped = is_seg_am_mapped(am, eu, mmu_idx); in get_seg_physical_address()
106 unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM; in get_segctl_physical_address() local
111 access_type, mmu_idx, am, eu, segmask, in get_segctl_physical_address()
176 unsigned int am = CP0SC_AM_UK; in get_physical_address() local
180 am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; in get_physical_address()
183 if (env->CP0_Status & am_ksux[am]) { in get_physical_address()
[all …]
/qemu/hw/misc/
H A Dmips_itu.c91 uint64_t *am = &tag->ITCAddressMap[0]; in itc_reconfigure() local
93 hwaddr address = am[0] & ITC_AM0_BASE_ADDRESS_MASK; in itc_reconfigure()
94 uint64_t size = (1 * KiB) + (am[1] & ITC_AM1_ADDR_MASK_MASK); in itc_reconfigure()
95 bool is_enabled = (am[0] & ITC_AM0_EN_MASK) != 0; in itc_reconfigure()
110 uint64_t *am = &tag->ITCAddressMap[0]; in itc_tag_write() local
126 am_old = am[index]; in itc_tag_write()
127 am[index] = (data & mask) | (am_old & ~mask); in itc_tag_write()
128 if (am_old != am[index]) { in itc_tag_write()
/qemu/target/hexagon/
H A Dgen_printinsn.py81 am = assign.match(t)
82 if am and len(am.group(0)) == me - ms:
/qemu/
H A D.b4-config10 am-perpatch-check-cmd = scripts/checkpatch.pl -q --terse --no-summary --mailback -
/qemu/hw/i386/
H A Dintel_iommu.c2453 uint8_t am, uint32_t pasid) in vtd_iotlb_page_invalidate_notify() argument
2458 hwaddr size = (1 << am) * VTD_PAGE_SIZE; in vtd_iotlb_page_invalidate_notify()
2515 hwaddr addr, uint8_t am) in vtd_iotlb_page_invalidate() argument
2519 trace_vtd_inv_desc_iotlb_pages(domain_id, addr, am); in vtd_iotlb_page_invalidate()
2521 assert(am <= VTD_MAMV); in vtd_iotlb_page_invalidate()
2524 info.mask = ~((1 << am) - 1); in vtd_iotlb_page_invalidate()
2528 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, PCI_NO_PASID); in vtd_iotlb_page_invalidate()
2541 uint8_t am; in vtd_iotlb_flush() local
2558 am = VTD_IVA_AM(addr); in vtd_iotlb_flush()
2560 if (am > VTD_MAMV) { in vtd_iotlb_flush()
[all …]
/qemu/docs/system/riscv/
H A Dvirt.rst182 $ git am riscv.patch
H A Dsifive_u.rst170 $ git am riscv.patch
/qemu/docs/devel/migration/
H A Dcompatibility.rst36 I am going to list the number of combinations that we can have. Let's
/qemu/target/i386/
H A Dcpu.c7282 X86CPUModel *am = g_new0(X86CPUModel, 1); in x86_register_cpudef_types() local
7283 am->cpudef = def; in x86_register_cpudef_types()
7284 am->version = vdef->version; in x86_register_cpudef_types()
7285 am->is_alias = true; in x86_register_cpudef_types()
7286 x86_register_cpu_model_type(vdef->alias, am); in x86_register_cpudef_types()