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Searched refs:addr_reg (Results 1 – 13 of 13) sorted by relevance

/qemu/target/riscv/
H A Dpmp.c194 target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg; in pmp_update_rule_addr()
200 prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg; in pmp_update_rule_addr()
532 if (env->pmp_state.pmp[addr_index].addr_reg == val) { in pmpaddr_csr_write()
553 env->pmp_state.pmp[addr_index].addr_reg = val; in pmpaddr_csr_write()
578 val = env->pmp_state.pmp[addr_index].addr_reg; in pmpaddr_csr_read()
H A Dpmp.h53 target_ulong addr_reg; member
H A Dmachine.c53 VMSTATE_UINTTL(addr_reg, pmp_entry_t),
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc1041 TCGReg addr_reg, MemOpIdx oi,
1062 ldst->addr_reg = addr_reg;
1067 tcg_out_opc_srli_d(s, TCG_REG_TMP2, addr_reg,
1089 tcg_out_addi(s, addr_type, TCG_REG_TMP1, addr_reg, s_mask - a_mask);
1091 tcg_out_mov(s, addr_type, TCG_REG_TMP1, addr_reg);
1107 ldst->addr_reg = addr_reg;
1115 tcg_out_opc_bstrpick_d(s, TCG_REG_TMP1, addr_reg, 0, a_bits - 1);
1126 tcg_out_ext32u(s, h->base, addr_reg);
1128 h->base = addr_reg;
1171 TCGReg addr_reg, MemOpIdx oi)
[all …]
/qemu/tcg/riscv/
H A Dtcg-target.c.inc1676 TCGReg addr_reg, MemOpIdx oi,
1701 ldst->addr_reg = addr_reg;
1708 tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP2, addr_reg,
1719 addr_adj = addr_reg;
1723 addr_adj, addr_reg, s_mask - a_mask);
1747 tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2);
1750 addr_reg, TCG_REG_TMP2);
1752 tcg_out_ext32u(s, TCG_REG_TMP0, addr_reg);
1764 ldst->addr_reg = addr_reg;
1770 tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_reg, a_mask);
[all …]
/qemu/tcg/s390x/
H A Dtcg-target.c.inc1980 TCGReg addr_reg, MemOpIdx oi,
2004 ldst->addr_reg = addr_reg;
2006 tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE,
2021 tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask);
2023 tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off);
2047 tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg);
2050 h->base = addr_reg;
2058 ldst->addr_reg = addr_reg;
2061 tcg_out_insn(s, RI, TMLL, addr_reg, a_mask);
2067 h->base = addr_reg;
[all …]
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc1645 TCGReg addr_reg, MemOpIdx oi,
1669 ldst->addr_reg = addr_reg;
1679 TCG_REG_TMP0, TCG_REG_TMP0, addr_reg,
1700 addr_adj = addr_reg;
1704 addr_adj, addr_reg, s_mask - a_mask);
1720 h->index = addr_reg;
1728 ldst->addr_reg = addr_reg;
1731 tcg_out_logicali(s, I3404_ANDSI, 0, TCG_REG_XZR, addr_reg, a_mask);
1740 h->index = addr_reg;
1743 h->base = addr_reg;
[all …]
/qemu/tcg/sparc64/
H A Dtcg-target.c.inc1092 TCGReg addr_reg, MemOpIdx oi,
1122 tcg_out_arithi(s, TCG_REG_T1, addr_reg,
1141 tcg_out_arithi(s, TCG_REG_T3, addr_reg, compare_mask, ARITH_AND);
1144 tcg_out_arith(s, TCG_REG_T3, addr_reg, TCG_REG_T3, ARITH_AND);
1151 ldst->addr_reg = addr_reg;
1166 tcg_out_arithi(s, TCG_REG_G0, addr_reg, a_mask, ARITH_ANDCC);
1171 ldst->addr_reg = addr_reg;
1182 tcg_out_ext32u(s, TCG_REG_T2, addr_reg);
1188 h->index = addr_reg;
/qemu/tcg/
H A Dtcg.c104 TCGReg addr_reg; /* reg index for guest virtual addr */ member
6604 ldst->addr_reg, -1); in tcg_out_ld_helper_args()
6612 ldst->addr_reg, -1); in tcg_out_ld_helper_args()
6779 ldst->addr_reg, -1); in tcg_out_st_helper_args()
6784 ldst->addr_reg, -1); in tcg_out_st_helper_args()
/qemu/tcg/ppc/
H A Dtcg-target.c.inc2434 ldst->addr_reg = addr;
2527 ldst->addr_reg = addr;
2644 TCGReg addr_reg, MemOpIdx oi, bool is_ld)
2652 ldst = prepare_host_addr(s, &h, addr_reg, oi, is_ld);
/qemu/tcg/mips/
H A Dtcg-target.c.inc1193 ldst->addr_reg = addr;
1256 ldst->addr_reg = addr;
/qemu/tcg/arm/
H A Dtcg-target.c.inc1421 ldst->addr_reg = addr;
1487 ldst->addr_reg = addr;
/qemu/tcg/i386/
H A Dtcg-target.c.inc2195 ldst->addr_reg = addr;
2249 ldst->addr_reg = addr;