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Searched refs:_bit (Results 1 – 25 of 54) sorted by relevance

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/linux/drivers/reset/sti/
H A Dreset-stih407.c18 #define STIH407_PDN_0(_bit) \ argument
19 _SYSCFG_RST_CH(stih407_core, SYSCFG_5000, _bit, SYSSTAT_5500, _bit)
20 #define STIH407_PDN_1(_bit) \ argument
21 _SYSCFG_RST_CH(stih407_core, SYSCFG_5001, _bit, SYSSTAT_5501, _bit)
22 #define STIH407_PDN_ETH(_bit, _stat) \ argument
23 _SYSCFG_RST_CH(stih407_sbc_reg, SYSCFG_4032, _bit, SYSSTAT_4520, _stat)
57 #define STIH407_SRST_CORE(_reg, _bit) \ argument
58 _SYSCFG_RST_CH_NO_ACK(stih407_core, _reg, _bit)
60 STIH407_SRST_SBC(_reg,_bit) global() argument
63 STIH407_SRST_LPM(_reg,_bit) global() argument
[all...]
/linux/sound/soc/mediatek/mt8188/
H A Dmt8188-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
33 .bit = _bit, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
49 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
51 GATE_AUD4(_id,_name,_parent,_bit) global() argument
54 GATE_AUD5(_id,_name,_parent,_bit) global() argument
57 GATE_AUD6(_id,_name,_parent,_bit) global() argument
[all...]
/linux/sound/soc/mediatek/mt8195/
H A Dmt8195-audsys-clk.c28 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
33 .bit = _bit, \
38 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
39 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
42 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
43 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
45 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
46 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
48 #define GATE_AUD3(_id, _name, _parent, _bit) \ argument
49 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON3, _bit)
51 GATE_AUD4(_id,_name,_parent,_bit) global() argument
54 GATE_AUD5(_id,_name,_parent,_bit) global() argument
57 GATE_AUD6(_id,_name,_parent,_bit) global() argument
[all...]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-audsys-clk.c27 #define GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, _flags, _cgflags) {\ argument
32 .bit = _bit, \
37 #define GATE_AFE(_id, _name, _parent, _reg, _bit) \ argument
38 GATE_AFE_FLAGS(_id, _name, _parent, _reg, _bit, \
41 #define GATE_AUD0(_id, _name, _parent, _bit) \ argument
42 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON0, _bit)
44 #define GATE_AUD1(_id, _name, _parent, _bit) \ argument
45 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON1, _bit)
47 #define GATE_AUD2(_id, _name, _parent, _bit) \ argument
48 GATE_AFE(_id, _name, _parent, AUDIO_TOP_CON2, _bit)
[all...]
/linux/drivers/clk/meson/
H A Dclk-regmap.h121 #define __MESON_PCLK(_name, _reg, _bit, _ops, _pname) \ argument
125 .bit_idx = (_bit), \
136 #define MESON_PCLK(_name, _reg, _bit, _pname) \ argument
137 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ops, _pname)
139 #define MESON_PCLK_RO(_name, _reg, _bit, _pname) \ argument
140 __MESON_PCLK(_name, _reg, _bit, &clk_regmap_gate_ro_ops, _pname)
H A Dgxbb-aoclk.c26 #define GXBB_AO_GATE(_name, _bit) \ argument
30 .bit_idx = (_bit), \
H A Daxg-aoclk.c37 #define AXG_AO_GATE(_name, _bit) \ argument
41 .bit_idx = (_bit), \
/linux/drivers/clk/renesas/
H A Drzg2l-cpg.h221 #define DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, _is_coupled) \ argument
228 .bit = (_bit), \
232 #define DEF_MOD(_name, _id, _parent, _off, _bit, _mstop_conf) \ argument
233 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, false)
235 #define DEF_COUPLED(_name, _id, _parent, _off, _bit, _mstop_conf) \ argument
236 DEF_MOD_BASE(_name, _id, _parent, _off, _bit, _mstop_conf, true)
251 #define DEF_RST_MON(_id, _off, _bit, _monbit) \ argument
254 .bit = (_bit), \
257 #define DEF_RST(_id, _off, _bit) \ argument
258 DEF_RST_MON(_id, _off, _bit,
[all...]
/linux/arch/xtensa/include/asm/
H A Dbitops.h102 static inline void arch_##op##_bit(unsigned int bit, volatile unsigned long *p)\
122 arch_test_and_##op##_bit(unsigned int bit, volatile unsigned long *p) \
145 static inline void arch_##op##_bit(unsigned int bit, volatile unsigned long *p)\
166 arch_test_and_##op##_bit(unsigned int bit, volatile unsigned long *p) \
/linux/drivers/pinctrl/mediatek/
H A Dpinctrl-mtk-common.h109 #define MTK_PIN_DRV_GRP(_pin, _offset, _bit, _grp) \ argument
113 .bit = _bit, \
157 #define MTK_PIN_IES_SMT_SPEC(_start, _end, _offset, _bit) \ argument
161 .bit = _bit, \
/linux/Documentation/
H A Datomic_bitops.txt20 {set,clear,change}_bit()
25 test_and_{set,clear,change}_bit()
47 The test_and_{}_bit() operations return the original value of the bit.
/linux/drivers/clk/bcm/
H A Dclk-kona.h91 #define POLICY(_offset, _bit) \ argument
94 .bit = (_bit), \
375 #define TRIGGER(_offset, _bit) \ argument
378 .bit = (_bit), \
434 #define CCU_LVM_EN(_offset, _bit) \ argument
437 .bit = (_bit), \
/linux/drivers/net/ethernet/mellanox/mlx5/core/steering/hws/
H A Dinternal.h36 #define IS_BIT_SET(_value, _bit) ((_value) & (1ULL << (_bit))) argument
/linux/drivers/reset/
H A Dreset-uniphier.c27 #define UNIPHIER_RESET(_id, _reg, _bit) \ argument
31 .bit = (_bit), \
34 #define UNIPHIER_RESETX(_id, _reg, _bit) \ argument
38 .bit = (_bit), \
/linux/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7366.c108 #define DIV4(_reg, _bit, _mask, _flags) \ argument
109 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
128 #define MSTP(_parent, _reg, _bit, _flags) \ argument
129 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
H A Dclock-sh7343.c105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
125 #define MSTP(_parent, _reg, _bit, _flags) \ argument
126 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
H A Dclock-shx3.c61 #define DIV4(_bit, _mask, _flags) \ argument
62 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
H A Dclock-sh7757.c62 #define DIV4(_bit, _mask, _flags) \ argument
63 SH_CLK_DIV4(&pll_clk, FRQCR, _bit, _mask, _flags)
H A Dclock-sh7785.c66 #define DIV4(_bit, _mask, _flags) \ argument
67 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
H A Dclock-sh7786.c67 #define DIV4(_bit, _mask, _flags) \ argument
68 SH_CLK_DIV4(&pll_clk, FRQMR1, _bit, _mask, _flags)
/linux/drivers/clk/mvebu/
H A Darmada-37xx-periph.c129 #define PERIPH_GATE(_name, _bit) \ argument
132 .bit_idx = _bit, \
181 #define PERIPH_CLK_FULL_DD(_name, _bit, _shift, _reg1, _reg2, _shift1, _shift2)\ argument
182 static PERIPH_GATE(_name, _bit); \
186 #define PERIPH_CLK_FULL(_name, _bit, _shift, _reg, _shift1, _table) \ argument
187 static PERIPH_GATE(_name, _bit); \
191 #define PERIPH_CLK_GATE_DIV(_name, _bit, _reg, _shift, _table) \ argument
192 static PERIPH_GATE(_name, _bit); \
/linux/drivers/clk/uniphier/
H A Dclk-uniphier.h95 #define UNIPHIER_CLK_GATE(_name, _idx, _parent, _reg, _bit) \ argument
103 .bit = (_bit), \
/linux/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7264.c77 #define DIV4(_reg, _bit, _mask, _flags) \ argument
78 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
H A Dclock-sh7269.c105 #define DIV4(_reg, _bit, _mask, _flags) \ argument
106 SH_CLK_DIV4(&pll_clk, _reg, _bit, _mask, _flags)
/linux/drivers/staging/rtl8723bs/hal/
H A Dodm_interface.h38 #define ODM_BIT(_name, _pDM_Odm) _cat(_name, _pDM_Odm->SupportICType, _bit)

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