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Searched refs:ZA (Results 1 – 8 of 8) sorted by relevance

/qemu/disas/
H A Dalpha.c320 #define ZA (FC + 1) macro
322 #define ZB (ZA + 1)
651 #define ARG_FPZ1 { ZA, FB, DFC1 }
656 #define ARG_OPRZ1 { ZA, RB, DRC1 }
657 #define ARG_OPRLZ1 { ZA, LIT, RC }
729 MEM_MASK, BASE, { ZA } }, /* pseudo */
801 { "nop", OPR(0x11,0x20), BASE, { ZA, ZB, ZC } }, /* pseudo */
802 { "clr", OPR(0x11,0x20), BASE, { ZA, ZB, RC } }, /* pseudo */
803 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
805 { "mov", OPRL(0x11,0x20), BASE, { ZA, LIT, RC } }, /* pseudo */
[all …]
/qemu/linux-user/aarch64/
H A Dtarget_prctl.h100 env->svcr = FIELD_DP64(env->svcr, SVCR, ZA, 0); in do_prctl_sme_set_vl()
H A Dsignal.c395 *svcr = FIELD_DP64(*svcr, SVCR, ZA, 1); in target_restore_za_record()
589 if (FIELD_EX64(env->svcr, SVCR, ZA)) { in target_setup_frame()
/qemu/target/arm/tcg/
H A Dhflags.c272 DP_TBFLAG_A64(flags, PSTATE_ZA, FIELD_EX64(env->svcr, SVCR, ZA)); in rebuild_hflags_a64()
H A Dtranslate-a64.c1516 if (FIELD_EX64(req, SVCR, ZA) && !s->pstate_za) { in sme_enabled_check_with_svcr()
/qemu/target/arm/
H A Dmachine.c309 return FIELD_EX64(cpu->env.svcr, SVCR, ZA); in za_needed()
H A Dcpu.c1224 (FIELD_EX64(env->svcr, SVCR, ZA) ? 'Z' : '-'), in aarch64_cpu_dump_state()
1324 FIELD_EX64(env->svcr, SVCR, ZA) && in aarch64_cpu_dump_state()
H A Dcpu.h1480 FIELD(SVCR, ZA, 1, 1)