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Searched refs:TM_WORD2 (Results 1 – 6 of 6) sorted by relevance

/qemu/tests/qtest/
H A Dpnv-xive2-test.c119 set_tima32(qts, i, TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | nvp_idx); in reset_pool_threads()
142 set_tima32(qts, i, TM_QW3_HV_PHYS + TM_WORD2, 0x80000000); in reset_hw_threads()
367 qw1w2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
368 qw2w2 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
369 qw3b8 = get_tima8(qts, target_pir, TM_QW3_HV_PHYS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
380 memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW1_OS + TM_WORD2], 4); in test_pull_thread_ctx_to_odd_thread_cl()
382 memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW2_HV_POOL + TM_WORD2], 4); in test_pull_thread_ctx_to_odd_thread_cl()
385 cl_pair[XIVE_ODD_CL + TM_QW3_HV_PHYS + TM_WORD2]); in test_pull_thread_ctx_to_odd_thread_cl()
388 word2 = get_tima32(qts, target_pir, TM_QW1_OS + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
390 word2 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
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/qemu/hw/intc/
H A Dxive2.c611 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); in xive2_tm_pull_ctx()
655 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80; in xive2_tm_report_line_gen1()
656 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; in xive2_tm_report_line_gen1()
657 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; in xive2_tm_report_line_gen1()
658 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3); in xive2_tm_report_line_gen1()
663 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) { in xive2_tm_report_line_gen1()
668 data[0xC] = regs[TM_QW0_USER + TM_WORD2]; in xive2_tm_report_line_gen1()
671 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1]; in xive2_tm_report_line_gen1()
672 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2]; in xive2_tm_report_line_gen1()
673 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3]; in xive2_tm_report_line_gen1()
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H A Dxive.c153 if (pool_regs[TM_WORD2] & 0x80) { in xive_tctx_set_cppr()
216 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); in xive_tm_pull_pool_ctx()
223 uint8_t qw3b8_prev = tctx->regs[TM_QW3_HV_PHYS + TM_WORD2]; in xive_tm_pull_phys_ctx()
227 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = qw3b8; in xive_tm_pull_phys_ctx()
234 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; in xive_tm_vt_push()
240 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; in xive_tm_vt_poll()
442 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
559 { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2, 4, xive_tm_push_os_ctx,
563 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push,
565 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, NULL,
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H A Dspapr_xive.c657 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); in xive_tctx_set_os_cam()
/qemu/include/hw/ppc/
H A Dxive_regs.h92 #define TM_WORD2 0x8 macro
H A Dxive.h365 return *((uint32_t *) &ring[TM_WORD2]); in xive_tctx_word2()