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Searched refs:TM_QW2_HV_POOL (Results 1 – 4 of 4) sorted by relevance

/qemu/tests/qtest/
H A Dpnv-xive2-test.c117 set_tima32(qts, i, TM_QW2_HV_POOL + TM_WORD0, 0x000000ff); in reset_pool_threads()
118 set_tima32(qts, i, TM_QW2_HV_POOL + TM_WORD1, 0); in reset_pool_threads()
119 set_tima32(qts, i, TM_QW2_HV_POOL + TM_WORD2, TM_QW2W2_VP | nvp_idx); in reset_pool_threads()
305 reg32 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0); in test_pool_irq()
325 reg32 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD0); in test_pool_irq()
368 qw2w2 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
382 memcpy(&cl_word, &cl_pair[XIVE_ODD_CL + TM_QW2_HV_POOL + TM_WORD2], 4); in test_pull_thread_ctx_to_odd_thread_cl()
390 word2 = get_tima32(qts, target_pir, TM_QW2_HV_POOL + TM_WORD2); in test_pull_thread_ctx_to_odd_thread_cl()
/qemu/hw/intc/
H A Dxive2.c651 data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB]; in xive2_tm_report_line_gen1()
656 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; in xive2_tm_report_line_gen1()
902 case TM_QW2_HV_POOL: in xive2_tctx_get_nvp_indexes()
955 uint8_t *pregs = &tctx->regs[TM_QW2_HV_POOL]; in xive2_tctx_set_cppr()
970 ring_min = TM_QW2_HV_POOL; in xive2_tctx_set_cppr()
979 ring_min = TM_QW2_HV_POOL; in xive2_tctx_set_cppr()
1200 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); in xive2_presenter_tctx_match()
1230 !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] == 0) && in xive2_presenter_tctx_match()
1234 return TM_QW2_HV_POOL; in xive2_presenter_tctx_match()
1263 uint8_t alt_ring = (ring == TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : ring; in xive2_tm_irq_precluded()
H A Dxive.c36 case TM_QW2_HV_POOL: in xive_tctx_output()
58 alt_ring = TM_QW2_HV_POOL; in xive_tctx_accept()
90 uint8_t alt_ring = (ring == TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : ring; in xive_tctx_notify()
99 case TM_QW2_HV_POOL: in xive_tctx_notify()
150 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; in xive_tctx_set_cppr()
163 ring_min = TM_QW2_HV_POOL; in xive_tctx_set_cppr()
178 uint8_t alt_ring = (ring == TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : ring; in xive_tctx_pipr_update()
212 uint32_t qw2w2_prev = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); in xive_tm_pull_pool_ctx()
216 memcpy(&tctx->regs[TM_QW2_HV_POOL + TM_WORD2], &qw2w2, 4); in xive_tm_pull_pool_ctx()
1737 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); in xive_presenter_tctx_match()
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/qemu/include/hw/ppc/
H A Dxive_regs.h69 #define TM_QW2_HV_POOL 0x020 /* Ring 0..1 */ macro