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Searched refs:TM_PIPR (Results 1 – 3 of 3) sorted by relevance

/qemu/hw/intc/
H A Dxive.c52 uint8_t cppr = regs[TM_PIPR]; in xive_tctx_accept()
80 alt_regs[TM_IPB], regs[TM_PIPR], in xive_tctx_accept()
94 if (alt_regs[TM_PIPR] < alt_regs[TM_CPPR]) { in xive_tctx_notify()
109 regs[TM_IPB], alt_regs[TM_PIPR], in xive_tctx_notify()
132 regs[TM_IPB], regs[TM_PIPR], in xive_tctx_set_cppr()
168 regs[TM_PIPR] = pipr_min; in xive_tctx_set_cppr()
185 alt_regs[TM_PIPR] = xive_ipb_to_pipr(regs[TM_IPB]); in xive_tctx_pipr_update()
188 alt_regs[TM_PIPR] = xive_priority_to_pipr(priority); in xive_tctx_pipr_update()
762 ring[TM_ACK_CNT], ring[TM_INC], ring[TM_AGE], ring[TM_PIPR], in xive_tctx_ring_print()
840 tctx->regs[TM_QW1_OS + TM_PIPR] = in xive_tctx_reset()
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H A Dxive2.c934 regs[TM_IPB], regs[TM_PIPR], in xive2_tctx_set_cppr()
984 regs[TM_PIPR] = pipr_min; in xive2_tctx_set_cppr()
1004 lsmfb_min < regs[TM_PIPR]) { in xive2_tctx_set_cppr()
1036 regs[TM_PIPR] = backlog_prio; in xive2_tctx_set_cppr()
/qemu/include/hw/ppc/
H A Dxive_regs.h82 #define TM_PIPR 0x7 /* - + - + */ macro