Searched refs:TM_NSR (Results 1 – 3 of 3) sorted by relevance
47 uint8_t nsr = regs[TM_NSR]; in xive_tctx_accept()51 if (regs[TM_NSR] != 0) { in xive_tctx_accept()70 if (regs[TM_NSR] & TM_NSR_GRP_LVL) { in xive_tctx_accept()71 regs[TM_NSR] &= ~TM_NSR_GRP_LVL; in xive_tctx_accept()77 regs[TM_NSR] = 0; in xive_tctx_accept()81 regs[TM_CPPR], regs[TM_NSR]); in xive_tctx_accept()97 regs[TM_NSR] = TM_QW1_NSR_EO | (group_level & 0x3F); in xive_tctx_notify()100 alt_regs[TM_NSR] = (TM_QW3_NSR_HE_POOL << 6) | (group_level & 0x3F); in xive_tctx_notify()103 regs[TM_NSR] = (TM_QW3_NSR_HE_PHYS << 6) | (group_level & 0x3F); in xive_tctx_notify()110 alt_regs[TM_CPPR], alt_regs[TM_NSR]); in xive_tctx_notify()[all …]
648 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR]; in xive2_tm_report_line_gen1()659 data[0x8] = regs[TM_QW1_OS + TM_NSR]; in xive2_tm_report_line_gen1()670 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80; in xive2_tm_report_line_gen1()935 cppr, regs[TM_NSR]); in xive2_tctx_set_cppr()
73 #define TM_NSR 0x0 /* + + - + */ macro