Home
last modified time | relevance | path

Searched refs:TCG_TYPE_V64 (Results 1 – 13 of 13) sorted by relevance

/qemu/tcg/
H A Dtcg-op-gvec.c468 tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { in choose_vector_type()
476 tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { in choose_vector_type()
480 && tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)) { in choose_vector_type()
481 return TCG_TYPE_V64; in choose_vector_type()
499 tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64); in do_dup_store()
519 case TCG_TYPE_V64: in do_dup_store()
521 tcg_gen_stl_vec(t_vec, tcg_env, dofs + i, TCG_TYPE_V64); in do_dup_store()
1235 case TCG_TYPE_V64: in tcg_gen_gvec_2()
1236 expand_2_vec(g->vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, in tcg_gen_gvec_2()
1299 case TCG_TYPE_V64: in tcg_gen_gvec_2i()
[all …]
H A Doptimize.c374 case TCG_TYPE_V64: in tcg_opt_gen_mov()
1116 case TCG_TYPE_V64: in fold_to_not()
1453 case TCG_TYPE_V64: in fold_andc()
1920 case TCG_TYPE_V64: in fold_eqv()
2260 case TCG_TYPE_V64: in fold_orc()
2682 case TCG_TYPE_V64: in fold_sub_to_neg()
H A Dtcg.c2147 case TCG_TYPE_V64: in tcg_temp_new_internal()
2232 case TCG_TYPE_V64: in tcg_temp_new_vec()
2429 case TCG_TYPE_V64: in tcg_op_supported()
2822 case TCG_TYPE_V64: in tcg_get_arg_str_ptr()
2826 64 << (ts->type - TCG_TYPE_V64), ts->val); in tcg_get_arg_str_ptr()
4574 case TCG_TYPE_V64: in temp_allocate_frame()
5926 tcg_out_vec_op(s, op->opc, type - TCG_TYPE_V64, in tcg_reg_alloc_op()
H A Dtcg-op-vec.c295 tcg_debug_assert(low_type >= TCG_TYPE_V64); in tcg_gen_stl_vec()
/qemu/include/tcg/
H A Dtcg.h142 TCG_TYPE_V64, enumerator
173 if (i >= TCG_TYPE_V64) { in tcg_type_size()
175 i -= TCG_TYPE_V64 - 1; in tcg_type_size()
/qemu/tcg/riscv/
H A Dtcg-target.c.inc391 if (type >= TCG_TYPE_V64) {
728 const VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew];
768 case TCG_TYPE_V64:
1000 case TCG_TYPE_V64:
1039 case TCG_TYPE_V64:
2650 TCGType type = vecl + TCG_TYPE_V64;
2997 VsetCache *p = &riscv_vset_cache[type - TCG_TYPE_V64][vsew];
3034 /* Match riscv_lg2_vlenb to TCG_TYPE_V64. */
3035 QEMU_BUILD_BUG_ON(TCG_TYPE_V64 != 3);
3037 for (TCGType t = TCG_TYPE_V64; t <= TCG_TYPE_V256; t++) {
[all …]
/qemu/tcg/arm/
H A Dtcg-target.c.inc2735 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
2766 case TCG_TYPE_V64:
2791 case TCG_TYPE_V64:
2823 case TCG_TYPE_V64:
2826 tcg_out_vreg3(s, INSN_VORR, type - TCG_TYPE_V64, 0, ret, arg, arg);
2874 tcg_out_mov(s, TCG_TYPE_V64, rd, rl);
2880 int q = type - TCG_TYPE_V64;
2886 tcg_out_mov(s, TCG_TYPE_V64, rd, rs);
2905 tcg_out_ld(s, TCG_TYPE_V64, rd, base, offset);
2910 int q = type - TCG_TYPE_V64;
[all …]
/qemu/tcg/loongarch64/
H A Dtcg-target.c.inc336 case TCG_TYPE_V64:
899 case TCG_TYPE_V64:
939 case TCG_TYPE_V64:
2187 TCGType type = vecl + TCG_TYPE_V64;
2695 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
/qemu/tcg/aarch64/
H A Dtcg-target.c.inc1061 int is_q = type - TCG_TYPE_V64;
1245 case TCG_TYPE_V64:
1275 case TCG_TYPE_V64:
1304 case TCG_TYPE_V64:
2930 TCGType type = vecl + TCG_TYPE_V64;
3393 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
/qemu/tcg/i386/
H A Dtcg-target.c.inc946 case TCG_TYPE_V64:
1055 if (type == TCG_TYPE_V64) {
1210 case TCG_TYPE_V64:
1255 case TCG_TYPE_V64:
3895 TCGType type = vecl + TCG_TYPE_V64;
3997 if (type != TCG_TYPE_V64) {
4501 case TCG_TYPE_V64:
4774 tcg_target_available_regs[TCG_TYPE_V64] = ALL_VECTOR_REGS;
/qemu/tcg/ppc/
H A Dtcg-target.c.inc887 case TCG_TYPE_V64:
1210 if (type == TCG_TYPE_V64) {
1228 load_insn = type == TCG_TYPE_V64 ? LXSDX : LXVDSX;
1551 case TCG_TYPE_V64:
1606 case TCG_TYPE_V64:
4180 TCGType type = vecl + TCG_TYPE_V64;
4507 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
/qemu/tcg/s390x/
H A Dtcg-target.c.inc905 case TCG_TYPE_V64:
1072 case TCG_TYPE_V64:
1105 case TCG_TYPE_V64:
3345 TCGType type = vecl + TCG_TYPE_V64;
3734 tcg_target_available_regs[TCG_TYPE_V64] = 0xffffffff00000000ull;
/qemu/docs/devel/
H A Dtcg-ops.rst136 * ``TCG_TYPE_V64``