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Searched refs:SR_MD (Results 1 – 5 of 5) sorted by relevance

/qemu/target/sh4/
H A Dhelper.c148 env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB); in superh_cpu_do_interrupt()
335 use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); in get_mmu_address()
341 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { in get_mmu_address()
351 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { in get_mmu_address()
369 if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) { in get_mmu_address()
401 if (!(env->sr & (1u << SR_MD)) in get_physical_address()
611 int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD)); in cpu_sh4_write_mmaped_utlb_addr()
741 int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD)); in cpu_sh4_is_cached()
744 if (env->sr & (1u << SR_MD)) { in cpu_sh4_is_cached()
H A Dgdbstub.c33 if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) { in superh_cpu_gdb_read_register()
82 if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) { in superh_cpu_gdb_write_register()
H A Dcpu.h39 #define SR_MD 30 macro
95 #define TB_FLAG_SR_MD (1 << SR_MD) /* 30 */
H A Dcpu.c126 return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0; in sh4_cpu_mmu_index()
147 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) | in superh_cpu_reset_hold()
H A Dtranslate.c56 #define IS_USER(ctx) (!(ctx->tbflags & (1u << SR_MD)))
2198 ctx->memidx = (tbflags & (1u << SR_MD)) == 0 ? 1 : 0; in sh4_tr_init_disas_context()
2204 ctx->gbank = ((tbflags & (1 << SR_MD)) && in sh4_tr_init_disas_context()