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Searched refs:SMT (Results 1 – 6 of 6) sorted by relevance

/qemu/tests/qtest/
H A Dpnv-xive2-test.c21 #define SMT 4 /* some tests will break if less than 4 */ macro
114 for (i = 0; i < SMT; i++) { in reset_pool_threads()
129 if (SMT >= 4) { in reset_hw_threads()
138 for (i = 0; i < SMT; i++) { in reset_hw_threads()
424 for (chosen_one = 0; chosen_one < SMT; chosen_one++) { in test_hw_group_irq()
431 g_assert_cmphex(chosen_one, <, SMT); in test_hw_group_irq()
483 for (i = 0; i < SMT; i++) { in test_hw_group_irq_backlog()
500 for (i = 0; i < SMT; i++) { in test_hw_group_irq_backlog()
554 SMT, SMT); in test_xive()
H A Dpnv-xscom.h12 #define SMT 4 /* some tests will break if less than 4 */ macro
H A Dpnv-host-i2c-test.c420 machine, SMT, SMT); in test_host_i2c()
/qemu/qapi/
H A Dmachine-common.json27 # @thread: thread level, which would also be called SMT level or
/qemu/docs/system/i386/
H A Dhyperv.rst189 physical core unless they are reported as sibling SMT threads. This information
190 is required by Windows and Hyper-V guests to properly mitigate SMT related CPU
196 setting also prevents migration as SMT settings on the destination may differ.
/qemu/disas/
H A Dmips.c1175 #define SMT INSN_SMARTMIPS macro
2535 {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT },
2558 {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
2605 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT },
2672 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
2737 {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
2788 {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT },
2826 {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT },
2827 {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT },
2828 {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT },
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