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Searched refs:SMSTATEEN0_HSENVCFG (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcsr.c3247 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in read_senvcfg()
3268 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in write_senvcfg()
3297 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in read_henvcfg()
3319 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in write_henvcfg()
3358 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in read_henvcfgh()
3376 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_HSENVCFG); in write_henvcfgh()
3409 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; in write_mstateen0()
3468 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; in write_mstateen0h()
3513 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; in write_hstateen0()
3573 uint64_t wr_mask = SMSTATEEN_STATEEN | SMSTATEEN0_HSENVCFG; in write_hstateen0h()
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H A Dcpu_bits.h364 #define SMSTATEEN0_HSENVCFG (1ULL << 62) macro