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Searched refs:SMSTATEEN0_AIA (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h362 #define SMSTATEEN0_AIA (1ULL << 59) macro
H A Dcsr.c364 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); in aia_smode()
382 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); in aia_smode32()
699 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); in aia_hmode()
717 ret = smstateen_acc_ok(env, 0, SMSTATEEN0_AIA); in aia_hmode32()
3428 wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); in write_mstateen0()
3529 wr_mask |= (SMSTATEEN0_AIA | SMSTATEEN0_IMSIC); in write_hstateen0()