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Searched refs:SHIFT (Results 1 – 25 of 26) sorted by relevance

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/qemu/ui/
H A Dcurses_keys.h36 #define SHIFT SCANCODE_SHIFT macro
133 ['!'] = 2 | SHIFT,
134 ['@'] = 3 | SHIFT,
135 ['#'] = 4 | SHIFT,
136 ['$'] = 5 | SHIFT,
137 ['%'] = 6 | SHIFT,
138 ['^'] = 7 | SHIFT,
139 ['&'] = 8 | SHIFT,
140 ['*'] = 9 | SHIFT,
141 ['('] = 10 | SHIFT,
[all …]
H A Dcurses.c365 if (keycode & SHIFT) { in curses_refresh()
399 if (keycode & SHIFT) { in curses_refresh()
/qemu/target/i386/
H A Dops_sse.h25 #if SHIFT == 0
40 #if SHIFT == 1
47 #define LANE_WIDTH (SHIFT ? 16 : 8)
50 #if SHIFT == 0
61 for (int i = 0; i < 1 << SHIFT; i++) { in glue()
66 for (int i = 0; i < 4 << SHIFT; i++) { in glue()
76 for (int i = 0; i < 1 << SHIFT; i++) { in glue()
81 for (int i = 0; i < 4 << SHIFT; i++) { in glue()
95 for (int i = 0; i < 4 << SHIFT; i++) { in glue()
104 for (int i = 0; i < 1 << SHIFT; i++) { in glue()
[all …]
H A Dhelper.h205 #define SHIFT 0 macro
207 #define SHIFT 1 macro
209 #define SHIFT 2 macro
/qemu/audio/
H A Dmixeng.c43 #define SHIFT 8 macro
50 #undef SHIFT
57 #define SHIFT 8 macro
63 #undef SHIFT
74 #define SHIFT 16 macro
90 #undef SHIFT
97 #define SHIFT 16 macro
112 #undef SHIFT
120 #define SHIFT 32 macro
136 #undef SHIFT
[all …]
H A Dmixeng_template.h78 return ((int64_t) nv) << (32 - SHIFT); in glue()
80 return ((int64_t) nv - HALF) << (32 - SHIFT); in glue()
93 return ENDIAN_CONVERT ((IN_T) (v >> (32 - SHIFT))); in glue()
95 return ENDIAN_CONVERT ((IN_T) ((v >> (32 - SHIFT)) + HALF)); in glue()
/qemu/target/i386/tcg/
H A Dops_sse_header.h.inc19 #if SHIFT == 0
24 #if SHIFT == 1
50 #if SHIFT >= 1
67 #if SHIFT == 0
80 #if SHIFT < 2
84 #if SHIFT == 0
92 #if SHIFT >= 1
104 #if SHIFT == 1
141 #if SHIFT == 1
176 #if SHIFT == 1
[all …]
H A Dcc_helper.c25 #define SHIFT 0 macro
27 #undef SHIFT
29 #define SHIFT 1 macro
31 #undef SHIFT
33 #define SHIFT 2 macro
35 #undef SHIFT
39 #define SHIFT 3 macro
41 #undef SHIFT
H A Dcc_helper_template.h.inc20 #define DATA_BITS (1 << (3 + SHIFT))
H A Dfpu_helper.c3313 #define SHIFT 0 macro
3316 #define SHIFT 1 macro
3319 #define SHIFT 2 macro
/qemu/hw/audio/
H A Dadlib.c52 #define SHIFT 1 macro
163 nbytes = samples << SHIFT; in write_audio()
166 s->mixbuf + (pos << (SHIFT - 1)), in write_audio()
171 wsampl = wbytes >> SHIFT; in write_audio()
191 samples = free >> SHIFT; in adlib_callback()
273 as.nchannels = SHIFT; in adlib_realizefn()
291 s->samples = AUD_get_buffer_size_out (s->voice) >> SHIFT; in adlib_realizefn()
292 s->mixbuf = g_malloc0 (s->samples << SHIFT); in adlib_realizefn()
/qemu/tests/tcg/hexagon/
H A Dload_align.c87 #define LOAD_ur(SZ, RES, SHIFT, IDX) \ argument
89 "%0 = mem" #SZ "_fifo(%1<<#" #SHIFT " + ##buf)\n\t" \
92 #define LOAD_ur_b(RES, SHIFT, IDX) \ argument
93 LOAD_ur(b, RES, SHIFT, IDX)
94 #define LOAD_ur_h(RES, SHIFT, IDX) \ argument
95 LOAD_ur(h, RES, SHIFT, IDX)
97 #define TEST_ur(NAME, SZ, SHIFT, RES1, RES2, RES3, RES4) \ argument
101 LOAD_ur_##SZ(result, (SHIFT), 0); \
103 LOAD_ur_##SZ(result, (SHIFT), 1); \
105 LOAD_ur_##SZ(result, (SHIFT), 2); \
[all …]
H A Dbrev.c112 #define TEST_BREV_LOAD(SZ, TYPE, BUF, SHIFT, EXP) \ argument
117 BREV_LOAD_##SZ(result, p, 1 << (SHIFT - NBITS)); \
122 #define TEST_BREV_STORE(SZ, TYPE, BUF, VAL, SHIFT) \ argument
127 BREV_STORE_##SZ(p, (TYPE)(VAL), 1 << (SHIFT - NBITS)); \
134 #define TEST_BREV_STORE_NEW(SZ, BUF, SHIFT) \ argument
139 BREV_STORE_##SZ(p, i, 1 << (SHIFT - NBITS)); \
H A Dload_unpack.c96 #define BxW_LOAD_ur(SZ, RES, SHIFT, IDX) \ argument
98 "%0 = mem" #SZ "(%1<<#" #SHIFT " + ##buf)\n\t" \
101 #define BxW_LOAD_ur_Z(RES, SHIFT, IDX) \ argument
102 BxW_LOAD_ur(ubh, RES, SHIFT, IDX)
103 #define BxW_LOAD_ur_S(RES, SHIFT, IDX) \ argument
104 BxW_LOAD_ur(bh, RES, SHIFT, IDX)
106 #define TEST_ur(NAME, TYPE, SIGN, SHIFT, EXT, RES1, RES2, RES3, RES4) \ argument
111 BxW_LOAD_ur_##SIGN(result, (SHIFT), 0); \
113 BxW_LOAD_ur_##SIGN(result, (SHIFT), 1); \
115 BxW_LOAD_ur_##SIGN(result, (SHIFT), 2); \
[all …]
H A Dcirc.c339 #define CIRC_TEST_STORE_IMM(SZ, CHK, TYPE, BUF, BUFSIZE, SHIFT, INC) \ argument
347 CIRC_STORE_IMM_##SZ(val << SHIFT, p, BUF, size * sizeof(TYPE), INC); \
355 CIRC_STORE_IMM_##SZ(val << SHIFT, p, BUF, size * sizeof(TYPE), \
371 #define CIRC_TEST_STORE_REG(SZ, CHK, TYPE, BUF, BUFSIZE, SHIFT) \ argument
379 CIRC_STORE_REG_##SZ(val << SHIFT, p, BUF, size * sizeof(TYPE), 1); \
387 CIRC_STORE_REG_##SZ(val << SHIFT, p, BUF, size * sizeof(TYPE), -1); \
/qemu/accel/tcg/
H A Datomic_template.h27 # define SHIFT 4 macro
33 # define SHIFT 3 macro
39 # define SHIFT 2 macro
45 # define SHIFT 1 macro
51 # define SHIFT 0 macro
331 #undef SHIFT
/qemu/target/hexagon/imported/
H A Dalu.idef1129 #define CROUND(DST,SRC,SHIFT) \
1133 if (SHIFT == 0) { \
1135 } else if ((SRC & (size8s_t)((1LL << (SHIFT - 1)) - 1LL)) == 0) { \
1138 rndbit_128 = fSHIFTL128(rndbit_128, SHIFT);\
1142 tmp128 = fSHIFTR128(tmp128, SHIFT);\
1145 rndbit_128 = fCAST8S_16S((1LL << (SHIFT - 1))); \
1148 tmp128 = fSHIFTR128(tmp128, SHIFT);\
1188 #define VRMINORMAX(TAG,STR,OP,SHORTTYPE,SETTYPE,GETTYPE,NEL,SHIFT) \
1198 addr = RuV | i<<SHIFT; \
1205 #define RMINMAX(SHORTTYPE,SETTYPE,GETTYPE,NEL,SHIFT) \
[all …]
H A Dmpy.idef916 #define VCMPYSEMI(DST,ACC0,ACC1,SHIFT,SAT) \
917 fSETWORD(0,DST,SAT(ACC0 fSCALE(SHIFT,fMPY16SS(fGETHALF(1,RssV),fGETHALF(0,RttV)) + \
919 fSETWORD(1,DST,SAT(ACC1 fSCALE(SHIFT,fMPY16SS(fGETHALF(3,RssV),fGETHALF(2,RttV)) + \
923 #define VCMPYSEMR(DST,ACC0,ACC1,SHIFT,SAT) \
924 fSETWORD(0,DST,SAT(ACC0 fSCALE(SHIFT,fMPY16SS(fGETHALF(0,RssV),fGETHALF(0,RttV)) - \
926 fSETWORD(1,DST,SAT(ACC1 fSCALE(SHIFT,fMPY16SS(fGETHALF(2,RssV),fGETHALF(2,RttV)) - \
/qemu/target/s390x/tcg/
H A Dinsn-data.h.inc815 /* SHIFT LEFT SINGLE */
819 /* SHIFT LEFT SINGLE LOGICAL */
823 /* SHIFT RIGHT SINGLE */
827 /* SHIFT RIGHT SINGLE LOGICAL */
831 /* SHIFT LEFT DOUBLE */
833 /* SHIFT LEFT DOUBLE LOGICAL */
835 /* SHIFT RIGHT DOUBLE */
837 /* SHIFT RIGHT DOUBLE LOGICAL */
1222 /* VECTOR ELEMENT SHIFT LEFT */
1225 /* VECTOR ELEMENT SHIFT RIGHT ARITHMETIC */
[all …]
/qemu/target/hexagon/
H A Dgen_tcg.h73 #define GET_EA_pcr(SHIFT) \ argument
77 gen_read_ireg(ireg, MuV, (SHIFT)); \
110 #define fGEN_TCG_LOAD_pcr(SHIFT, LOAD) \ argument
114 gen_read_ireg(ireg, MuV, SHIFT); \
422 #define fGEN_TCG_STORE_pcr(SHIFT, STORE) \ argument
428 gen_read_ireg(ireg, MuV, SHIFT); \
/qemu/include/hw/
H A Dregisterfields.h165 enum { name ## _ ## SHIFT = (shift)}; \
/qemu/target/arm/tcg/
H A Dmve_helper.c2096 #define DO_SHL(N, SHIFT) ((N) << (SHIFT)) argument
2097 #define DO_SHR(N, SHIFT) ((N) >> (SHIFT)) argument
2098 #define SHL_MASK(EBITS, SHIFT) MAKE_64BIT_MASK((SHIFT), (EBITS) - (SHIFT)) argument
2099 #define SHR_MASK(EBITS, SHIFT) MAKE_64BIT_MASK(0, (EBITS) - (SHIFT)) argument
H A Dsve_helper.c2266 #define DO_BINOPNB(NAME, TYPEW, TYPEN, SHIFT, OP) \ argument
2273 *(TYPEW *)(vd + i) = (TYPEN)OP(nn, mm, SHIFT); \
2277 #define DO_BINOPNT(NAME, TYPEW, TYPEN, SHIFT, HW, HN, OP) \ argument
2284 *(TYPEN *)(vd + HN(i + sizeof(TYPEN))) = OP(nn, mm, SHIFT); \
/qemu/target/hexagon/imported/mmvec/
H A Dext.idef339 #define VALIGNB(SHIFT) \
342 VdV.ub[i] = (i+SHIFT>=fVBYTES()) ? VuV.ub[i+SHIFT-fVBYTES()] : VvV.ub[i+SHIFT];\
944 * MMVECTOR SHIFT AND PERMUTE
/qemu/target/mips/tcg/
H A Dnanomips_translate.c.inc210 /* P16.SHIFT instruction pool */
413 /* P.SHIFT instruction pool */

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