Home
last modified time | relevance | path

Searched refs:SCTRDEPTH_MASK (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A Dcpu_bits.h936 #define SCTRDEPTH_MASK 0x7 macro
H A Dcsr.c2525 const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_ctrsource()
2564 const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_ctrtarget()
2604 const uint64_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_ctrdata()
4303 uint64_t mask = wr_mask & SCTRDEPTH_MASK; in rmw_sctrdepth()
4313 uint64_t depth = get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_sctrdepth()
4317 env->sctrdepth = set_field(env->sctrdepth, SCTRDEPTH_MASK, depth); in rmw_sctrdepth()
4333 uint32_t depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in rmw_sctrstatus()
H A Dcpu_helper.c1007 depth = 16 << get_field(env->sctrdepth, SCTRDEPTH_MASK); in riscv_ctr_add_entry()