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Searched refs:RV_MAX_TRIGGERS (Results 1 – 5 of 5) sorted by relevance

/qemu/target/riscv/
H A Ddebug.c174 if (val < RV_MAX_TRIGGERS) { in tselect_csr_write()
703 for (int i = 0; i < RV_MAX_TRIGGERS; i++) { in riscv_itrigger_enabled()
723 for (int i = 0; i < RV_MAX_TRIGGERS; i++) { in helper_itrigger_match()
752 for (int i = 0; i < RV_MAX_TRIGGERS; i++) { in riscv_itrigger_update_count()
952 for (i = 0; i < RV_MAX_TRIGGERS; i++) { in riscv_cpu_debug_check_breakpoint()
998 for (i = 0; i < RV_MAX_TRIGGERS; i++) { in riscv_cpu_debug_check_watchpoint()
1051 for (i = 0; i < RV_MAX_TRIGGERS; i++) { in riscv_trigger_realize()
1063 for (i = 0; i < RV_MAX_TRIGGERS; i++) { in riscv_trigger_reset_hold()
H A Dcpu.h436 target_ulong tdata1[RV_MAX_TRIGGERS];
437 target_ulong tdata2[RV_MAX_TRIGGERS];
438 target_ulong tdata3[RV_MAX_TRIGGERS];
440 struct CPUBreakpoint *cpu_breakpoint[RV_MAX_TRIGGERS];
441 struct CPUWatchpoint *cpu_watchpoint[RV_MAX_TRIGGERS];
442 QEMUTimer *itrigger_timer[RV_MAX_TRIGGERS];
H A Dmachine.c246 VMSTATE_UINTTL_ARRAY(env.tdata1, RISCVCPU, RV_MAX_TRIGGERS),
247 VMSTATE_UINTTL_ARRAY(env.tdata2, RISCVCPU, RV_MAX_TRIGGERS),
248 VMSTATE_UINTTL_ARRAY(env.tdata3, RISCVCPU, RV_MAX_TRIGGERS),
H A Ddebug.h27 #define RV_MAX_TRIGGERS 2 macro
H A Dcsr.c5290 if (env->trigger_cur >= RV_MAX_TRIGGERS && csrno == CSR_TDATA1) { in read_tdata()