Home
last modified time | relevance | path

Searched refs:RVV (Results 1 – 9 of 9) sorted by relevance

/qemu/target/riscv/kvm/
H A Dkvm-cpu.c155 KVM_MISA_CFG(RVV, KVM_RISCV_ISA_EXT_V),
845 if (!riscv_has_ext(env, RVV)) { in kvm_riscv_get_regs_vector()
901 if (!riscv_has_ext(env, RVV)) { in kvm_riscv_put_regs_vector()
1285 if (riscv_has_ext(&cpu->env, RVV)) { in kvm_riscv_init_cfg()
1979 if (riscv_has_ext(&cpu->env, RVV)) { in kvm_cpu_realize()
2001 !riscv_has_ext(env, RVV)) { in riscv_kvm_cpu_finalize_features()
2049 if (riscv_has_ext(env, RVV) && riscv_cpu_option_set("vlen")) { in riscv_kvm_cpu_finalize_features()
/qemu/target/riscv/
H A Dcpu.c43 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
604 if (riscv_has_ext(env, RVV) && (flags & CPU_DUMP_VPU)) { in riscv_cpu_dump_state()
1167 MISA_EXT_INFO(RVV, "v", "Vector operations"),
2064 .misa_ext = RVV,
2156 .ext = RVV,
3054 .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,
H A Dmachine.c133 return riscv_has_ext(env, RVV); in vector_needed()
H A Dcpu.h65 #define RVV RV('V') macro
H A Dcsr.c2001 if (riscv_has_ext(env, RVV)) { in write_mstatus()
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c654 if (riscv_has_ext(env, RVV)) { in riscv_cpu_validate_set_extensions()
1290 MISA_CFG(RVV, false),
1582 riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); in riscv_init_max_cpu_extensions()
/qemu/target/riscv/insn_trans/
H A Dtrans_rvv.c.inc657 * In cpu_get_tb_cpu_state(), set VILL if RVV was not present.
658 * So RVV is also be checked in this function.
2308 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
2321 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
2519 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
2530 (!has_ext(s, RVV) ? s->sew != MO_64 : true);
/qemu/tcg/riscv/
H A Dtcg-target.c.inc676 * With RVV 1.0, vs2 is the first operand, while rs1/imm is the
/qemu/linux-user/
H A Dsyscall.c9042 value |= riscv_has_ext(env, RVV) ? in risc_hwprobe_fill_pairs()