Home
last modified time | relevance | path

Searched refs:RVI (Results 1 – 7 of 7) sorted by relevance

/qemu/target/riscv/tcg/
H A Dtcg-cpu.c506 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; in riscv_cpu_validate_g()
590 if (riscv_has_ext(env, RVI) && riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
596 if (!riscv_has_ext(env, RVI) && !riscv_has_ext(env, RVE)) { in riscv_cpu_validate_set_extensions()
608 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { in riscv_cpu_validate_set_extensions()
1284 MISA_CFG(RVI, true),
1386 if (bit == RVI && !profile->enabled) { in cpu_set_profile()
/qemu/target/riscv/
H A Dcpu.c43 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
1161 MISA_EXT_INFO(RVI, "i", "Base integer instruction set"),
2010 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
2935 .misa_ext = RVI | RVM | RVA | RVC | RVU,
2944 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
2963 .misa_ext = RVI | RVM | RVC | RVU,
2991 .misa_ext = RVI
3178 .misa_ext = RVI
H A Dxthead.decode50 # the regular RVI `add` instruction.
H A Dcpu.h59 #define RVI RV('I') macro
H A Dcsr.c2143 if (!(val & RVI && val & RVM && val & RVA && in write_misa()
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c153 KVM_MISA_CFG(RVI, KVM_RISCV_ISA_EXT_I),
/qemu/linux-user/
H A Dsyscall.c9030 value = riscv_has_ext(env, RVI) && in risc_hwprobe_fill_pairs()