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Searched refs:RVH (Results 1 – 11 of 11) sorted by relevance

/qemu/target/riscv/insn_trans/
H A Dtrans_rvh.c.inc67 REQUIRE_EXT(ctx, RVH);
73 REQUIRE_EXT(ctx, RVH);
79 REQUIRE_EXT(ctx, RVH);
85 REQUIRE_EXT(ctx, RVH);
91 REQUIRE_EXT(ctx, RVH);
97 REQUIRE_EXT(ctx, RVH);
103 REQUIRE_EXT(ctx, RVH);
109 REQUIRE_EXT(ctx, RVH);
116 REQUIRE_EXT(ctx, RVH);
123 REQUIRE_EXT(ctx, RVH);
[all …]
H A Dtrans_svinval.c.inc58 REQUIRE_EXT(ctx, RVH);
71 REQUIRE_EXT(ctx, RVH);
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c352 if (!cpu_misa_ext_is_user_set(RVH)) { in riscv_cpu_enable_named_feat()
353 riscv_cpu_write_misa_bit(cpu, RVH, true); in riscv_cpu_enable_named_feat()
410 if (riscv_has_ext(env, RVH) && env->priv_ver < PRIV_VERSION_1_12_0) { in riscv_cpu_validate_misa_priv()
497 cpu->cfg.ext_sha = riscv_has_ext(&cpu->env, RVH) && in riscv_cpu_update_named_features()
608 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVI)) { in riscv_cpu_validate_set_extensions()
614 if (riscv_has_ext(env, RVH) && !riscv_has_ext(env, RVS)) { in riscv_cpu_validate_set_extensions()
1207 if (riscv_has_ext(env, RVH)) { in riscv_tcg_cpu_realize()
1250 if (misa_bit == RVH && env->priv_ver < PRIV_VERSION_1_12_0) { in cpu_set_misa_ext_cfg()
1289 MISA_CFG(RVH, true),
/qemu/target/riscv/
H A Dop_helper.c306 if (riscv_has_ext(env, RVH)) { in helper_sret()
324 if (riscv_has_ext(env, RVH) && !env->virt_enabled) { in helper_sret()
419 if (riscv_has_ext(env, RVH) && prev_virt) { in helper_mret()
470 if (riscv_has_ext(env, RVH) && prev_virt) { in helper_mnret()
H A Dcpu_helper.c610 g_assert(riscv_has_ext(env, RVH)); in riscv_cpu_swap_hypervisor_regs()
667 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_get_geilen()
676 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_geilen()
1057 if (riscv_has_ext(env, RVH)) { in riscv_cpu_set_mode()
2299 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
2321 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
2390 if (riscv_has_ext(env, RVH)) { in riscv_cpu_do_interrupt()
H A Dcsr.c440 if (riscv_has_ext(env, RVH)) { in hmode()
1073 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfg()
1075 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfg()
1099 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfgh()
1101 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mcyclecfgh()
1126 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_minstretcfg()
1128 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_minstretcfg()
1150 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_minstretcfgh()
1152 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_minstretcfgh()
1184 inh_avail_mask |= (riscv_has_ext(env, RVH) && in write_mhpmevent()
[all …]
H A Dcpu.c44 RVC, RVS, RVU, RVH, RVG, RVB, 0};
524 if (riscv_has_ext(env, RVH)) { in riscv_cpu_dump_state()
705 if (riscv_has_ext(env, RVH)) { in riscv_cpu_reset_hold()
749 if (riscv_has_ext(env, RVH)) { in riscv_cpu_reset_hold()
1051 if (!riscv_has_ext(env, RVH)) { in riscv_cpu_set_irq()
1166 MISA_EXT_INFO(RVH, "h", "Hypervisor"),
3054 .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,
3114 .misa_ext = RVG | RVC | RVS | RVU | RVH,
H A Dgdbstub.c243 if (riscv_has_ext(env, RVH) && new_virt != env->virt_enabled) { in riscv_gdb_set_virtual()
H A Dmachine.c77 return riscv_has_ext(env, RVH); in hyper_needed()
H A Dcpu.h69 #define RVH RV('H') macro
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c152 KVM_MISA_CFG(RVH, KVM_RISCV_ISA_EXT_H),