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Searched refs:RVF (Results 1 – 13 of 13) sorted by relevance

/qemu/target/riscv/insn_trans/
H A Dtrans_rvzfa.c.inc35 REQUIRE_EXT(ctx, RVF);
184 REQUIRE_EXT(ctx, RVF);
201 REQUIRE_EXT(ctx, RVF);
286 REQUIRE_EXT(ctx, RVF);
303 REQUIRE_EXT(ctx, RVF);
437 REQUIRE_EXT(ctx, RVF);
452 REQUIRE_EXT(ctx, RVF);
H A Dtrans_rvf.c.inc30 REQUIRE_EXT(ctx, RVF); \
36 if (!has_ext(ctx, RVF) || !has_ext(ctx, RVC)) { \
49 REQUIRE_EXT(ctx, RVF);
71 REQUIRE_EXT(ctx, RVF);
H A Dtrans_xthead.c.inc389 REQUIRE_EXT(ctx, RVF);
405 REQUIRE_EXT(ctx, RVF);
421 REQUIRE_EXT(ctx, RVF);
437 REQUIRE_EXT(ctx, RVF);
H A Dtrans_rvv.c.inc2557 * As RVF-only cpus always have values NaN-boxed to 64-bits,
2558 * RVF and RVD can be treated equally.
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c175 if (!riscv_has_ext(env, RVF)) { in riscv_get_tb_cpu_state()
506 uint32_t g_misa_bits[] = {RVI, RVM, RVA, RVF, RVD}; in riscv_cpu_validate_g()
619 if (riscv_has_ext(env, RVF) && !cpu->cfg.ext_zicsr) { in riscv_cpu_validate_set_extensions()
634 if (cpu->cfg.ext_zfa && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
639 if (cpu->cfg.ext_zfhmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
644 if (cpu->cfg.ext_zfbfmin && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
649 if (riscv_has_ext(env, RVD) && !riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
672 if (!riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
708 if (riscv_has_ext(env, RVF)) { in riscv_cpu_validate_set_extensions()
725 if (!riscv_has_ext(env, RVF) && cpu->cfg.ext_zcf) { in riscv_cpu_validate_set_extensions()
[all …]
/qemu/target/riscv/
H A Dgdbstub.c120 if (env->misa_ext & RVF) { in riscv_gdb_get_fpu()
351 } else if (env->misa_ext & RVF) { in riscv_cpu_register_gdb_regs_for_features()
H A Dcpu.c43 const uint32_t misa_bits[] = {RVI, RVE, RVM, RVA, RVF, RVD, RVV,
1160 MISA_EXT_INFO(RVF, "f", "Single-precision float point"),
2010 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
2130 .implied_misa_exts = RVF,
2136 .ext = RVF,
2195 .implied_misa_exts = RVF,
2232 .implied_misa_exts = RVF,
2238 .implied_misa_exts = RVF,
2253 .implied_misa_exts = RVF,
2345 .implied_misa_exts = RVF,
[all …]
H A Dcsr.c861 if (riscv_has_ext(env, RVF)) { in write_fflags()
880 if (riscv_has_ext(env, RVF)) { in write_frm()
900 if (riscv_has_ext(env, RVF)) { in write_fcsr()
1998 if (riscv_has_ext(env, RVF)) { in write_mstatus()
2144 val & RVF && val & RVD)) { in write_misa()
2166 if (!(env->misa_ext & RVF)) { in write_misa()
3410 if (!riscv_has_ext(env, RVF)) { in write_mstateen0()
3515 if (!riscv_has_ext(env, RVF)) { in write_hstateen0()
3626 if (!riscv_has_ext(env, RVF)) { in write_sstateen0()
H A Dcpu.h63 #define RVF RV('F') macro
H A Dtranslate.c673 if (!has_ext(ctx, RVF)) { in mark_fs_dirty()
H A Dcpu_helper.c596 if (riscv_has_ext(env, RVF)) { in riscv_cpu_swap_hypervisor_regs()
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c151 KVM_MISA_CFG(RVF, KVM_RISCV_ISA_EXT_F),
727 if (riscv_has_ext(env, RVF)) { in kvm_riscv_get_regs_fp()
760 if (riscv_has_ext(env, RVF)) { in kvm_riscv_put_regs_fp()
/qemu/linux-user/
H A Dsyscall.c9037 value = riscv_has_ext(env, RVF) && in risc_hwprobe_fill_pairs()