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Searched refs:RVC (Results 1 – 10 of 10) sorted by relevance

/qemu/target/riscv/
H A Dcpu.c44 RVC, RVS, RVU, RVH, RVG, RVB, 0};
1158 MISA_EXT_INFO(RVC, "c", "Compressed instructions"),
2010 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVB | RVU,
2935 .misa_ext = RVI | RVM | RVA | RVC | RVU,
2944 .misa_ext = RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU,
2963 .misa_ext = RVI | RVM | RVC | RVU,
3026 .misa_ext = RVG | RVC | RVS | RVU,
3054 .misa_ext = RVG | RVC | RVS | RVU | RVH | RVV,
3114 .misa_ext = RVG | RVC | RVS | RVU | RVH,
3149 .misa_ext = RVG | RVC | RVB | RVS | RVU,
H A Dcpu.h66 #define RVC RV('C') macro
798 return misa_ext & RVC; in riscv_cpu_allow_16bit_insn()
H A Dtranslate.c1231 if ((has_ext(ctx, RVC) || ctx->cfg_ptr->ext_zca) && in decode_opc()
H A Dcsr.c2138 if ((val & RVC) && (get_next_pc(env, ra) & 3) != 0) { in write_misa()
2139 val &= ~RVC; in write_misa()
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1061 if (riscv_has_ext(env, RVC) && env->priv_ver >= PRIV_VERSION_1_12_0) { in cpu_enable_zc_implied_rules()
1281 MISA_CFG(RVC, true),
/qemu/target/riscv/insn_trans/
H A Dtrans_rvf.c.inc36 if (!has_ext(ctx, RVF) || !has_ext(ctx, RVC)) { \
H A Dtrans_rvd.c.inc36 if (!has_ext(ctx, RVD) || !has_ext(ctx, RVC)) { \
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c149 KVM_MISA_CFG(RVC, KVM_RISCV_ISA_EXT_C),
/qemu/tcg/riscv/
H A Dtcg-target.c.inc429 * RISC-V immediate and instruction encoders (excludes 16-bit RVC)
/qemu/linux-user/
H A Dsyscall.c9040 value |= riscv_has_ext(env, RVC) ? in risc_hwprobe_fill_pairs()