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Searched refs:RV (Results 1 – 2 of 2) sorted by relevance

/qemu/target/riscv/
H A Dcpu.h53 #define RV(x) ((target_ulong)1 << (x - 'A')) macro
59 #define RVI RV('I')
60 #define RVE RV('E') /* E and I are mutually exclusive */
61 #define RVM RV('M')
62 #define RVA RV('A')
63 #define RVF RV('F')
64 #define RVD RV('D')
65 #define RVV RV('V')
66 #define RVC RV('C')
67 #define RVS RV('S')
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H A Dcpu.c2785 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { in riscv_isa_string()
2803 if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { in riscv_isa_extensions_list()