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Searched refs:RISCV_IOMMU_REG_IOHPMEVT_BASE (Results 1 – 3 of 3) sorted by relevance

/qemu/hw/riscv/
H A Driscv-iommu-hpm.c79 RISCV_IOMMU_REG_IOHPMEVT_BASE + off, in hpm_incr_ctr()
116 RISCV_IOMMU_REG_IOHPMEVT_BASE + (ctr_idx << 3)); in riscv_iommu_hpm_incr_ctr()
355 const uint32_t ctr_idx = (evt_reg - RISCV_IOMMU_REG_IOHPMEVT_BASE) >> 3; in riscv_iommu_process_hpmevt_write()
H A Driscv-iommu-bits.h222 #define RISCV_IOMMU_REG_IOHPMEVT_BASE 0x0160 macro
224 (RISCV_IOMMU_REG_IOHPMEVT_BASE + (_n * 0x8))
H A Driscv-iommu.c2042 case RISCV_IOMMU_REG_IOHPMEVT_BASE ... in riscv_iommu_process_hpm_writes()
2425 memset(&s->regs_ro[RISCV_IOMMU_REG_IOHPMEVT_BASE], in riscv_iommu_realize()