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Searched refs:RISCV_IOMMU_REG_IOHPMCTR_BASE (Results 1 – 3 of 3) sorted by relevance

/qemu/hw/riscv/
H A Driscv-iommu-hpm.c63 cntr_val = ldq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off]); in hpm_incr_ctr()
64 stq_le_p(&s->regs_rw[RISCV_IOMMU_REG_IOHPMCTR_BASE + off], cntr_val + 1); in hpm_incr_ctr()
H A Driscv-iommu-bits.h217 #define RISCV_IOMMU_REG_IOHPMCTR_BASE 0x0068 macro
219 (RISCV_IOMMU_REG_IOHPMCTR_BASE + (_n * 0x8))
H A Driscv-iommu.c2423 memset(&s->regs_ro[RISCV_IOMMU_REG_IOHPMCTR_BASE], in riscv_iommu_realize()