Searched refs:RISCV_IOMMU_QUEUE_INTR_ENABLE (Results 1 – 2 of 2) sorted by relevance
32 #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1) macro47 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE53 #define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE59 #define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE
67 #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1) macro161 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE172 #define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE181 #define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE