Searched refs:RISCV_IOMMU_QUEUE_ENABLE (Results 1 – 2 of 2) sorted by relevance
31 #define RISCV_IOMMU_QUEUE_ENABLE BIT(0) macro46 #define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE52 #define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE58 #define RISCV_IOMMU_PQCSR_PQEN RISCV_IOMMU_QUEUE_ENABLE
66 #define RISCV_IOMMU_QUEUE_ENABLE BIT(0) macro160 #define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE171 #define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE180 #define RISCV_IOMMU_PQCSR_PQEN RISCV_IOMMU_QUEUE_ENABLE