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Searched refs:RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED (Results 1 – 2 of 2) sorted by relevance

/qemu/hw/riscv/
H A Driscv-iommu.c321 return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED; in riscv_iommu_spa_fetch()
328 return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED; in riscv_iommu_spa_fetch()
341 return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED; in riscv_iommu_spa_fetch()
350 return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED; in riscv_iommu_spa_fetch()
359 return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED; in riscv_iommu_spa_fetch()
366 return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED; in riscv_iommu_spa_fetch()
527 case RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED: in riscv_iommu_report_fault()
921 return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED; in riscv_iommu_ctx_fetch()
961 return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED; in riscv_iommu_ctx_fetch()
991 return RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED; in riscv_iommu_ctx_fetch()
H A Driscv-iommu-bits.h394 RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED = 259, enumerator