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Searched refs:RISCV_IOMMU_FQCSR_FQEN (Results 1 – 4 of 4) sorted by relevance

/qemu/tests/qtest/
H A Driscv-iommu-test.c71 g_assert_cmpuint(reg & RISCV_IOMMU_FQCSR_FQEN, ==, 0); in test_reg_reset()
175 reg |= RISCV_IOMMU_FQCSR_FQEN; in test_iommu_init_queues()
/qemu/tests/qtest/libqos/
H A Driscv-iommu.h52 #define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE macro
/qemu/hw/riscv/
H A Driscv-iommu-bits.h171 #define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE macro
H A Driscv-iommu.c1853 bool enable = !!(ctrl_set & RISCV_IOMMU_FQCSR_FQEN); in riscv_iommu_process_fq_control()
2482 reg_clr = RISCV_IOMMU_FQCSR_FQEN | RISCV_IOMMU_FQCSR_FIE | in riscv_iommu_reset()