1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright © 2022-2023 Rivos Inc. 4 * Copyright © 2023 FORTH-ICS/CARV 5 * Copyright © 2023 RISC-V IOMMU Task Group 6 * 7 * RISC-V IOMMU - Register Layout and Data Structures. 8 * 9 * Based on the IOMMU spec version 1.0, 3/2023 10 * https://github.com/riscv-non-isa/riscv-iommu 11 */ 12 13 #ifndef HW_RISCV_IOMMU_BITS_H 14 #define HW_RISCV_IOMMU_BITS_H 15 16 #define RISCV_IOMMU_SPEC_DOT_VER 0x010 17 18 #ifndef GENMASK_ULL 19 #define GENMASK_ULL(h, l) (((~0ULL) >> (63 - (h) + (l))) << (l)) 20 #endif 21 22 /* 23 * struct riscv_iommu_fq_record - Fault/Event Queue Record 24 * See section 3.2 for more info. 25 */ 26 struct riscv_iommu_fq_record { 27 uint64_t hdr; 28 uint64_t _reserved; 29 uint64_t iotval; 30 uint64_t iotval2; 31 }; 32 /* Header fields */ 33 #define RISCV_IOMMU_FQ_HDR_CAUSE GENMASK_ULL(11, 0) 34 #define RISCV_IOMMU_FQ_HDR_PID GENMASK_ULL(31, 12) 35 #define RISCV_IOMMU_FQ_HDR_PV BIT_ULL(32) 36 #define RISCV_IOMMU_FQ_HDR_TTYPE GENMASK_ULL(39, 34) 37 #define RISCV_IOMMU_FQ_HDR_DID GENMASK_ULL(63, 40) 38 39 /* 40 * struct riscv_iommu_pq_record - PCIe Page Request record 41 * For more infos on the PCIe Page Request queue see chapter 3.3. 42 */ 43 struct riscv_iommu_pq_record { 44 uint64_t hdr; 45 uint64_t payload; 46 }; 47 /* Header fields */ 48 #define RISCV_IOMMU_PREQ_HDR_PID GENMASK_ULL(31, 12) 49 #define RISCV_IOMMU_PREQ_HDR_PV BIT_ULL(32) 50 #define RISCV_IOMMU_PREQ_HDR_PRIV BIT_ULL(33) 51 #define RISCV_IOMMU_PREQ_HDR_EXEC BIT_ULL(34) 52 #define RISCV_IOMMU_PREQ_HDR_DID GENMASK_ULL(63, 40) 53 54 /* Payload fields */ 55 #define RISCV_IOMMU_PREQ_PAYLOAD_R BIT_ULL(0) 56 #define RISCV_IOMMU_PREQ_PAYLOAD_W BIT_ULL(1) 57 #define RISCV_IOMMU_PREQ_PAYLOAD_L BIT_ULL(2) 58 #define RISCV_IOMMU_PREQ_PAYLOAD_M GENMASK_ULL(2, 0) 59 #define RISCV_IOMMU_PREQ_PRG_INDEX GENMASK_ULL(11, 3) 60 #define RISCV_IOMMU_PREQ_UADDR GENMASK_ULL(63, 12) 61 62 /* Common field positions */ 63 #define RISCV_IOMMU_PPN_FIELD GENMASK_ULL(53, 10) 64 #define RISCV_IOMMU_QUEUE_LOGSZ_FIELD GENMASK_ULL(4, 0) 65 #define RISCV_IOMMU_QUEUE_INDEX_FIELD GENMASK_ULL(31, 0) 66 #define RISCV_IOMMU_QUEUE_ENABLE BIT(0) 67 #define RISCV_IOMMU_QUEUE_INTR_ENABLE BIT(1) 68 #define RISCV_IOMMU_QUEUE_MEM_FAULT BIT(8) 69 #define RISCV_IOMMU_QUEUE_OVERFLOW BIT(9) 70 #define RISCV_IOMMU_QUEUE_ACTIVE BIT(16) 71 #define RISCV_IOMMU_QUEUE_BUSY BIT(17) 72 #define RISCV_IOMMU_ATP_PPN_FIELD GENMASK_ULL(43, 0) 73 #define RISCV_IOMMU_ATP_MODE_FIELD GENMASK_ULL(63, 60) 74 75 /* 5.3 IOMMU Capabilities (64bits) */ 76 #define RISCV_IOMMU_REG_CAP 0x0000 77 #define RISCV_IOMMU_CAP_VERSION GENMASK_ULL(7, 0) 78 #define RISCV_IOMMU_CAP_SV32 BIT_ULL(8) 79 #define RISCV_IOMMU_CAP_SV39 BIT_ULL(9) 80 #define RISCV_IOMMU_CAP_SV48 BIT_ULL(10) 81 #define RISCV_IOMMU_CAP_SV57 BIT_ULL(11) 82 #define RISCV_IOMMU_CAP_SV32X4 BIT_ULL(16) 83 #define RISCV_IOMMU_CAP_SV39X4 BIT_ULL(17) 84 #define RISCV_IOMMU_CAP_SV48X4 BIT_ULL(18) 85 #define RISCV_IOMMU_CAP_SV57X4 BIT_ULL(19) 86 #define RISCV_IOMMU_CAP_MSI_FLAT BIT_ULL(22) 87 #define RISCV_IOMMU_CAP_MSI_MRIF BIT_ULL(23) 88 #define RISCV_IOMMU_CAP_ATS BIT_ULL(25) 89 #define RISCV_IOMMU_CAP_T2GPA BIT_ULL(26) 90 #define RISCV_IOMMU_CAP_IGS GENMASK_ULL(29, 28) 91 #define RISCV_IOMMU_CAP_HPM BIT_ULL(30) 92 #define RISCV_IOMMU_CAP_DBG BIT_ULL(31) 93 #define RISCV_IOMMU_CAP_PAS GENMASK_ULL(37, 32) 94 #define RISCV_IOMMU_CAP_PD8 BIT_ULL(38) 95 #define RISCV_IOMMU_CAP_PD17 BIT_ULL(39) 96 #define RISCV_IOMMU_CAP_PD20 BIT_ULL(40) 97 98 enum riscv_iommu_igs_modes { 99 RISCV_IOMMU_CAP_IGS_MSI = 0, 100 RISCV_IOMMU_CAP_IGS_WSI, 101 RISCV_IOMMU_CAP_IGS_BOTH 102 }; 103 104 /* 5.4 Features control register (32bits) */ 105 #define RISCV_IOMMU_REG_FCTL 0x0008 106 #define RISCV_IOMMU_FCTL_BE BIT(0) 107 #define RISCV_IOMMU_FCTL_WSI BIT(1) 108 #define RISCV_IOMMU_FCTL_GXL BIT(2) 109 110 /* 5.5 Device-directory-table pointer (64bits) */ 111 #define RISCV_IOMMU_REG_DDTP 0x0010 112 #define RISCV_IOMMU_DDTP_MODE GENMASK_ULL(3, 0) 113 #define RISCV_IOMMU_DDTP_BUSY BIT_ULL(4) 114 #define RISCV_IOMMU_DDTP_PPN RISCV_IOMMU_PPN_FIELD 115 116 enum riscv_iommu_ddtp_modes { 117 RISCV_IOMMU_DDTP_MODE_OFF = 0, 118 RISCV_IOMMU_DDTP_MODE_BARE = 1, 119 RISCV_IOMMU_DDTP_MODE_1LVL = 2, 120 RISCV_IOMMU_DDTP_MODE_2LVL = 3, 121 RISCV_IOMMU_DDTP_MODE_3LVL = 4, 122 RISCV_IOMMU_DDTP_MODE_MAX = 4 123 }; 124 125 /* 5.6 Command Queue Base (64bits) */ 126 #define RISCV_IOMMU_REG_CQB 0x0018 127 #define RISCV_IOMMU_CQB_LOG2SZ RISCV_IOMMU_QUEUE_LOGSZ_FIELD 128 #define RISCV_IOMMU_CQB_PPN RISCV_IOMMU_PPN_FIELD 129 130 /* 5.7 Command Queue head (32bits) */ 131 #define RISCV_IOMMU_REG_CQH 0x0020 132 133 /* 5.8 Command Queue tail (32bits) */ 134 #define RISCV_IOMMU_REG_CQT 0x0024 135 136 /* 5.9 Fault Queue Base (64bits) */ 137 #define RISCV_IOMMU_REG_FQB 0x0028 138 #define RISCV_IOMMU_FQB_LOG2SZ RISCV_IOMMU_QUEUE_LOGSZ_FIELD 139 #define RISCV_IOMMU_FQB_PPN RISCV_IOMMU_PPN_FIELD 140 141 /* 5.10 Fault Queue Head (32bits) */ 142 #define RISCV_IOMMU_REG_FQH 0x0030 143 144 /* 5.11 Fault Queue tail (32bits) */ 145 #define RISCV_IOMMU_REG_FQT 0x0034 146 147 /* 5.12 Page Request Queue base (64bits) */ 148 #define RISCV_IOMMU_REG_PQB 0x0038 149 #define RISCV_IOMMU_PQB_LOG2SZ RISCV_IOMMU_QUEUE_LOGSZ_FIELD 150 #define RISCV_IOMMU_PQB_PPN RISCV_IOMMU_PPN_FIELD 151 152 /* 5.13 Page Request Queue head (32bits) */ 153 #define RISCV_IOMMU_REG_PQH 0x0040 154 155 /* 5.14 Page Request Queue tail (32bits) */ 156 #define RISCV_IOMMU_REG_PQT 0x0044 157 158 /* 5.15 Command Queue CSR (32bits) */ 159 #define RISCV_IOMMU_REG_CQCSR 0x0048 160 #define RISCV_IOMMU_CQCSR_CQEN RISCV_IOMMU_QUEUE_ENABLE 161 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE 162 #define RISCV_IOMMU_CQCSR_CQMF RISCV_IOMMU_QUEUE_MEM_FAULT 163 #define RISCV_IOMMU_CQCSR_CMD_TO BIT(9) 164 #define RISCV_IOMMU_CQCSR_CMD_ILL BIT(10) 165 #define RISCV_IOMMU_CQCSR_FENCE_W_IP BIT(11) 166 #define RISCV_IOMMU_CQCSR_CQON RISCV_IOMMU_QUEUE_ACTIVE 167 #define RISCV_IOMMU_CQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 168 169 /* 5.16 Fault Queue CSR (32bits) */ 170 #define RISCV_IOMMU_REG_FQCSR 0x004C 171 #define RISCV_IOMMU_FQCSR_FQEN RISCV_IOMMU_QUEUE_ENABLE 172 #define RISCV_IOMMU_FQCSR_FIE RISCV_IOMMU_QUEUE_INTR_ENABLE 173 #define RISCV_IOMMU_FQCSR_FQMF RISCV_IOMMU_QUEUE_MEM_FAULT 174 #define RISCV_IOMMU_FQCSR_FQOF RISCV_IOMMU_QUEUE_OVERFLOW 175 #define RISCV_IOMMU_FQCSR_FQON RISCV_IOMMU_QUEUE_ACTIVE 176 #define RISCV_IOMMU_FQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 177 178 /* 5.17 Page Request Queue CSR (32bits) */ 179 #define RISCV_IOMMU_REG_PQCSR 0x0050 180 #define RISCV_IOMMU_PQCSR_PQEN RISCV_IOMMU_QUEUE_ENABLE 181 #define RISCV_IOMMU_PQCSR_PIE RISCV_IOMMU_QUEUE_INTR_ENABLE 182 #define RISCV_IOMMU_PQCSR_PQMF RISCV_IOMMU_QUEUE_MEM_FAULT 183 #define RISCV_IOMMU_PQCSR_PQOF RISCV_IOMMU_QUEUE_OVERFLOW 184 #define RISCV_IOMMU_PQCSR_PQON RISCV_IOMMU_QUEUE_ACTIVE 185 #define RISCV_IOMMU_PQCSR_BUSY RISCV_IOMMU_QUEUE_BUSY 186 187 /* 5.18 Interrupt Pending Status (32bits) */ 188 #define RISCV_IOMMU_REG_IPSR 0x0054 189 #define RISCV_IOMMU_IPSR_CIP BIT(0) 190 #define RISCV_IOMMU_IPSR_FIP BIT(1) 191 #define RISCV_IOMMU_IPSR_PIP BIT(3) 192 193 enum { 194 RISCV_IOMMU_INTR_CQ, 195 RISCV_IOMMU_INTR_FQ, 196 RISCV_IOMMU_INTR_PM, 197 RISCV_IOMMU_INTR_PQ, 198 RISCV_IOMMU_INTR_COUNT 199 }; 200 201 #define RISCV_IOMMU_IOCOUNT_NUM 31 202 203 /* 5.19 Performance monitoring counter overflow status (32bits) */ 204 #define RISCV_IOMMU_REG_IOCOUNTOVF 0x0058 205 #define RISCV_IOMMU_IOCOUNTOVF_CY BIT(0) 206 207 /* 5.20 Performance monitoring counter inhibits (32bits) */ 208 #define RISCV_IOMMU_REG_IOCOUNTINH 0x005C 209 #define RISCV_IOMMU_IOCOUNTINH_CY BIT(0) 210 211 /* 5.21 Performance monitoring cycles counter (64bits) */ 212 #define RISCV_IOMMU_REG_IOHPMCYCLES 0x0060 213 #define RISCV_IOMMU_IOHPMCYCLES_COUNTER GENMASK_ULL(62, 0) 214 #define RISCV_IOMMU_IOHPMCYCLES_OVF BIT_ULL(63) 215 216 /* 5.22 Performance monitoring event counters (31 * 64bits) */ 217 #define RISCV_IOMMU_REG_IOHPMCTR_BASE 0x0068 218 #define RISCV_IOMMU_REG_IOHPMCTR(_n) \ 219 (RISCV_IOMMU_REG_IOHPMCTR_BASE + (_n * 0x8)) 220 221 /* 5.23 Performance monitoring event selectors (31 * 64bits) */ 222 #define RISCV_IOMMU_REG_IOHPMEVT_BASE 0x0160 223 #define RISCV_IOMMU_REG_IOHPMEVT(_n) \ 224 (RISCV_IOMMU_REG_IOHPMEVT_BASE + (_n * 0x8)) 225 #define RISCV_IOMMU_IOHPMEVT_EVENT_ID GENMASK_ULL(14, 0) 226 #define RISCV_IOMMU_IOHPMEVT_DMASK BIT_ULL(15) 227 #define RISCV_IOMMU_IOHPMEVT_PID_PSCID GENMASK_ULL(35, 16) 228 #define RISCV_IOMMU_IOHPMEVT_DID_GSCID GENMASK_ULL(59, 36) 229 #define RISCV_IOMMU_IOHPMEVT_PV_PSCV BIT_ULL(60) 230 #define RISCV_IOMMU_IOHPMEVT_DV_GSCV BIT_ULL(61) 231 #define RISCV_IOMMU_IOHPMEVT_IDT BIT_ULL(62) 232 #define RISCV_IOMMU_IOHPMEVT_OF BIT_ULL(63) 233 234 enum RISCV_IOMMU_HPMEVENT_id { 235 RISCV_IOMMU_HPMEVENT_INVALID = 0, 236 RISCV_IOMMU_HPMEVENT_URQ = 1, 237 RISCV_IOMMU_HPMEVENT_TRQ = 2, 238 RISCV_IOMMU_HPMEVENT_ATS_RQ = 3, 239 RISCV_IOMMU_HPMEVENT_TLB_MISS = 4, 240 RISCV_IOMMU_HPMEVENT_DD_WALK = 5, 241 RISCV_IOMMU_HPMEVENT_PD_WALK = 6, 242 RISCV_IOMMU_HPMEVENT_S_VS_WALKS = 7, 243 RISCV_IOMMU_HPMEVENT_G_WALKS = 8, 244 RISCV_IOMMU_HPMEVENT_MAX = 9 245 }; 246 247 /* 5.24 Translation request IOVA (64bits) */ 248 #define RISCV_IOMMU_REG_TR_REQ_IOVA 0x0258 249 250 /* 5.25 Translation request control (64bits) */ 251 #define RISCV_IOMMU_REG_TR_REQ_CTL 0x0260 252 #define RISCV_IOMMU_TR_REQ_CTL_GO_BUSY BIT_ULL(0) 253 #define RISCV_IOMMU_TR_REQ_CTL_NW BIT_ULL(3) 254 #define RISCV_IOMMU_TR_REQ_CTL_PID GENMASK_ULL(31, 12) 255 #define RISCV_IOMMU_TR_REQ_CTL_DID GENMASK_ULL(63, 40) 256 257 /* 5.26 Translation request response (64bits) */ 258 #define RISCV_IOMMU_REG_TR_RESPONSE 0x0268 259 #define RISCV_IOMMU_TR_RESPONSE_FAULT BIT_ULL(0) 260 #define RISCV_IOMMU_TR_RESPONSE_S BIT_ULL(9) 261 #define RISCV_IOMMU_TR_RESPONSE_PPN RISCV_IOMMU_PPN_FIELD 262 263 /* 5.27 Interrupt cause to vector (64bits) */ 264 #define RISCV_IOMMU_REG_ICVEC 0x02F8 265 #define RISCV_IOMMU_ICVEC_CIV GENMASK_ULL(3, 0) 266 #define RISCV_IOMMU_ICVEC_FIV GENMASK_ULL(7, 4) 267 #define RISCV_IOMMU_ICVEC_PMIV GENMASK_ULL(11, 8) 268 #define RISCV_IOMMU_ICVEC_PIV GENMASK_ULL(15, 12) 269 270 /* 5.28 MSI Configuration table (32 * 64bits) */ 271 #define RISCV_IOMMU_REG_MSI_CONFIG 0x0300 272 273 #define RISCV_IOMMU_REG_SIZE 0x1000 274 275 #define RISCV_IOMMU_DDTE_VALID BIT_ULL(0) 276 #define RISCV_IOMMU_DDTE_PPN RISCV_IOMMU_PPN_FIELD 277 278 /* Struct riscv_iommu_dc - Device Context - section 2.1 */ 279 struct riscv_iommu_dc { 280 uint64_t tc; 281 uint64_t iohgatp; 282 uint64_t ta; 283 uint64_t fsc; 284 uint64_t msiptp; 285 uint64_t msi_addr_mask; 286 uint64_t msi_addr_pattern; 287 uint64_t _reserved; 288 }; 289 290 /* Translation control fields */ 291 #define RISCV_IOMMU_DC_TC_V BIT_ULL(0) 292 #define RISCV_IOMMU_DC_TC_EN_ATS BIT_ULL(1) 293 #define RISCV_IOMMU_DC_TC_EN_PRI BIT_ULL(2) 294 #define RISCV_IOMMU_DC_TC_T2GPA BIT_ULL(3) 295 #define RISCV_IOMMU_DC_TC_DTF BIT_ULL(4) 296 #define RISCV_IOMMU_DC_TC_PDTV BIT_ULL(5) 297 #define RISCV_IOMMU_DC_TC_PRPR BIT_ULL(6) 298 #define RISCV_IOMMU_DC_TC_GADE BIT_ULL(7) 299 #define RISCV_IOMMU_DC_TC_SADE BIT_ULL(8) 300 #define RISCV_IOMMU_DC_TC_DPE BIT_ULL(9) 301 #define RISCV_IOMMU_DC_TC_SBE BIT_ULL(10) 302 #define RISCV_IOMMU_DC_TC_SXL BIT_ULL(11) 303 304 /* Second-stage (aka G-stage) context fields */ 305 #define RISCV_IOMMU_DC_IOHGATP_PPN RISCV_IOMMU_ATP_PPN_FIELD 306 #define RISCV_IOMMU_DC_IOHGATP_GSCID GENMASK_ULL(59, 44) 307 #define RISCV_IOMMU_DC_IOHGATP_MODE RISCV_IOMMU_ATP_MODE_FIELD 308 309 enum riscv_iommu_dc_iohgatp_modes { 310 RISCV_IOMMU_DC_IOHGATP_MODE_BARE = 0, 311 RISCV_IOMMU_DC_IOHGATP_MODE_SV32X4 = 8, 312 RISCV_IOMMU_DC_IOHGATP_MODE_SV39X4 = 8, 313 RISCV_IOMMU_DC_IOHGATP_MODE_SV48X4 = 9, 314 RISCV_IOMMU_DC_IOHGATP_MODE_SV57X4 = 10 315 }; 316 317 /* Translation attributes fields */ 318 #define RISCV_IOMMU_DC_TA_PSCID GENMASK_ULL(31, 12) 319 320 /* First-stage context fields */ 321 #define RISCV_IOMMU_DC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD 322 #define RISCV_IOMMU_DC_FSC_MODE RISCV_IOMMU_ATP_MODE_FIELD 323 324 /* Generic I/O MMU command structure - check section 3.1 */ 325 struct riscv_iommu_command { 326 uint64_t dword0; 327 uint64_t dword1; 328 }; 329 330 #define RISCV_IOMMU_CMD_OPCODE GENMASK_ULL(6, 0) 331 #define RISCV_IOMMU_CMD_FUNC GENMASK_ULL(9, 7) 332 333 #define RISCV_IOMMU_CMD_IOTINVAL_OPCODE 1 334 #define RISCV_IOMMU_CMD_IOTINVAL_FUNC_VMA 0 335 #define RISCV_IOMMU_CMD_IOTINVAL_FUNC_GVMA 1 336 #define RISCV_IOMMU_CMD_IOTINVAL_AV BIT_ULL(10) 337 #define RISCV_IOMMU_CMD_IOTINVAL_PSCID GENMASK_ULL(31, 12) 338 #define RISCV_IOMMU_CMD_IOTINVAL_PSCV BIT_ULL(32) 339 #define RISCV_IOMMU_CMD_IOTINVAL_GV BIT_ULL(33) 340 #define RISCV_IOMMU_CMD_IOTINVAL_GSCID GENMASK_ULL(59, 44) 341 342 #define RISCV_IOMMU_CMD_IOFENCE_OPCODE 2 343 #define RISCV_IOMMU_CMD_IOFENCE_FUNC_C 0 344 #define RISCV_IOMMU_CMD_IOFENCE_AV BIT_ULL(10) 345 #define RISCV_IOMMU_CMD_IOFENCE_DATA GENMASK_ULL(63, 32) 346 347 #define RISCV_IOMMU_CMD_IODIR_OPCODE 3 348 #define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_DDT 0 349 #define RISCV_IOMMU_CMD_IODIR_FUNC_INVAL_PDT 1 350 #define RISCV_IOMMU_CMD_IODIR_PID GENMASK_ULL(31, 12) 351 #define RISCV_IOMMU_CMD_IODIR_DV BIT_ULL(33) 352 #define RISCV_IOMMU_CMD_IODIR_DID GENMASK_ULL(63, 40) 353 354 /* 3.1.4 I/O MMU PCIe ATS */ 355 #define RISCV_IOMMU_CMD_ATS_OPCODE 4 356 #define RISCV_IOMMU_CMD_ATS_FUNC_INVAL 0 357 #define RISCV_IOMMU_CMD_ATS_FUNC_PRGR 1 358 #define RISCV_IOMMU_CMD_ATS_PID GENMASK_ULL(31, 12) 359 #define RISCV_IOMMU_CMD_ATS_PV BIT_ULL(32) 360 #define RISCV_IOMMU_CMD_ATS_DSV BIT_ULL(33) 361 #define RISCV_IOMMU_CMD_ATS_RID GENMASK_ULL(55, 40) 362 #define RISCV_IOMMU_CMD_ATS_DSEG GENMASK_ULL(63, 56) 363 /* dword1 is the ATS payload, two different payload types for INVAL and PRGR */ 364 365 /* ATS.PRGR payload */ 366 #define RISCV_IOMMU_CMD_ATS_PRGR_RESP_CODE GENMASK_ULL(47, 44) 367 368 enum riscv_iommu_dc_fsc_atp_modes { 369 RISCV_IOMMU_DC_FSC_MODE_BARE = 0, 370 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32 = 8, 371 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV39 = 8, 372 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV48 = 9, 373 RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV57 = 10, 374 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD8 = 1, 375 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD17 = 2, 376 RISCV_IOMMU_DC_FSC_PDTP_MODE_PD20 = 3 377 }; 378 379 enum riscv_iommu_fq_causes { 380 RISCV_IOMMU_FQ_CAUSE_INST_FAULT = 1, 381 RISCV_IOMMU_FQ_CAUSE_RD_ADDR_MISALIGNED = 4, 382 RISCV_IOMMU_FQ_CAUSE_RD_FAULT = 5, 383 RISCV_IOMMU_FQ_CAUSE_WR_ADDR_MISALIGNED = 6, 384 RISCV_IOMMU_FQ_CAUSE_WR_FAULT = 7, 385 RISCV_IOMMU_FQ_CAUSE_INST_FAULT_S = 12, 386 RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S = 13, 387 RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S = 15, 388 RISCV_IOMMU_FQ_CAUSE_INST_FAULT_VS = 20, 389 RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS = 21, 390 RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS = 23, 391 RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED = 256, 392 RISCV_IOMMU_FQ_CAUSE_DDT_LOAD_FAULT = 257, 393 RISCV_IOMMU_FQ_CAUSE_DDT_INVALID = 258, 394 RISCV_IOMMU_FQ_CAUSE_DDT_MISCONFIGURED = 259, 395 RISCV_IOMMU_FQ_CAUSE_TTYPE_BLOCKED = 260, 396 RISCV_IOMMU_FQ_CAUSE_MSI_LOAD_FAULT = 261, 397 RISCV_IOMMU_FQ_CAUSE_MSI_INVALID = 262, 398 RISCV_IOMMU_FQ_CAUSE_MSI_MISCONFIGURED = 263, 399 RISCV_IOMMU_FQ_CAUSE_MRIF_FAULT = 264, 400 RISCV_IOMMU_FQ_CAUSE_PDT_LOAD_FAULT = 265, 401 RISCV_IOMMU_FQ_CAUSE_PDT_INVALID = 266, 402 RISCV_IOMMU_FQ_CAUSE_PDT_MISCONFIGURED = 267, 403 RISCV_IOMMU_FQ_CAUSE_DDT_CORRUPTED = 268, 404 RISCV_IOMMU_FQ_CAUSE_PDT_CORRUPTED = 269, 405 RISCV_IOMMU_FQ_CAUSE_MSI_PT_CORRUPTED = 270, 406 RISCV_IOMMU_FQ_CAUSE_MRIF_CORRUIPTED = 271, 407 RISCV_IOMMU_FQ_CAUSE_INTERNAL_DP_ERROR = 272, 408 RISCV_IOMMU_FQ_CAUSE_MSI_WR_FAULT = 273, 409 RISCV_IOMMU_FQ_CAUSE_PT_CORRUPTED = 274 410 }; 411 412 /* MSI page table pointer */ 413 #define RISCV_IOMMU_DC_MSIPTP_PPN RISCV_IOMMU_ATP_PPN_FIELD 414 #define RISCV_IOMMU_DC_MSIPTP_MODE RISCV_IOMMU_ATP_MODE_FIELD 415 #define RISCV_IOMMU_DC_MSIPTP_MODE_OFF 0 416 #define RISCV_IOMMU_DC_MSIPTP_MODE_FLAT 1 417 418 /* 2.2 Process Directory Table */ 419 #define RISCV_IOMMU_PDTE_VALID BIT_ULL(0) 420 #define RISCV_IOMMU_PDTE_PPN RISCV_IOMMU_PPN_FIELD 421 422 /* Translation attributes fields */ 423 #define RISCV_IOMMU_PC_TA_V BIT_ULL(0) 424 #define RISCV_IOMMU_PC_TA_RESERVED GENMASK_ULL(63, 32) 425 426 /* First stage context fields */ 427 #define RISCV_IOMMU_PC_FSC_PPN RISCV_IOMMU_ATP_PPN_FIELD 428 #define RISCV_IOMMU_PC_FSC_RESERVED GENMASK_ULL(59, 44) 429 430 enum riscv_iommu_fq_ttypes { 431 RISCV_IOMMU_FQ_TTYPE_NONE = 0, 432 RISCV_IOMMU_FQ_TTYPE_UADDR_INST_FETCH = 1, 433 RISCV_IOMMU_FQ_TTYPE_UADDR_RD = 2, 434 RISCV_IOMMU_FQ_TTYPE_UADDR_WR = 3, 435 RISCV_IOMMU_FQ_TTYPE_TADDR_INST_FETCH = 5, 436 RISCV_IOMMU_FQ_TTYPE_TADDR_RD = 6, 437 RISCV_IOMMU_FQ_TTYPE_TADDR_WR = 7, 438 RISCV_IOMMU_FQ_TTYPE_PCIE_ATS_REQ = 8, 439 RISCV_IOMMU_FW_TTYPE_PCIE_MSG_REQ = 9, 440 }; 441 442 /* 443 * struct riscv_iommu_msi_pte - MSI Page Table Entry 444 */ 445 struct riscv_iommu_msi_pte { 446 uint64_t pte; 447 uint64_t mrif_info; 448 }; 449 450 /* Fields on pte */ 451 #define RISCV_IOMMU_MSI_PTE_V BIT_ULL(0) 452 #define RISCV_IOMMU_MSI_PTE_M GENMASK_ULL(2, 1) 453 454 #define RISCV_IOMMU_MSI_PTE_M_MRIF 1 455 #define RISCV_IOMMU_MSI_PTE_M_BASIC 3 456 457 /* When M == 1 (MRIF mode) */ 458 #define RISCV_IOMMU_MSI_PTE_MRIF_ADDR GENMASK_ULL(53, 7) 459 /* When M == 3 (basic mode) */ 460 #define RISCV_IOMMU_MSI_PTE_PPN RISCV_IOMMU_PPN_FIELD 461 #define RISCV_IOMMU_MSI_PTE_C BIT_ULL(63) 462 463 /* Fields on mrif_info */ 464 #define RISCV_IOMMU_MSI_MRIF_NID GENMASK_ULL(9, 0) 465 #define RISCV_IOMMU_MSI_MRIF_NPPN RISCV_IOMMU_PPN_FIELD 466 #define RISCV_IOMMU_MSI_MRIF_NID_MSB BIT_ULL(60) 467 468 #endif /* _RISCV_IOMMU_BITS_H_ */ 469