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Searched refs:RISCV_IOMMU_DDTP_MODE (Results 1 – 4 of 4) sorted by relevance

/qemu/tests/qtest/libqos/
H A Driscv-iommu.h42 #define RISCV_IOMMU_DDTP_MODE GENMASK_ULL(3, 0) macro
/qemu/tests/qtest/
H A Driscv-iommu-test.c84 g_assert_cmpuint(reg & RISCV_IOMMU_DDTP_MODE, ==, in test_reg_reset()
/qemu/hw/riscv/
H A Driscv-iommu.c879 unsigned mode = get_field(ddtp, RISCV_IOMMU_DDTP_MODE); in riscv_iommu_ctx_fetch()
1599 unsigned new_mode = get_field(new_ddtp, RISCV_IOMMU_DDTP_MODE); in riscv_iommu_process_ddtp()
1600 unsigned old_mode = get_field(old_ddtp, RISCV_IOMMU_DDTP_MODE); in riscv_iommu_process_ddtp()
1622 RISCV_IOMMU_DDTP_MODE, new_mode); in riscv_iommu_process_ddtp()
2371 s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ? in riscv_iommu_realize()
2388 ~(RISCV_IOMMU_DDTP_PPN | RISCV_IOMMU_DDTP_MODE)); in riscv_iommu_realize()
2475 s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, ddtp_mode); in riscv_iommu_reset()
H A Driscv-iommu-bits.h112 #define RISCV_IOMMU_DDTP_MODE GENMASK_ULL(3, 0) macro