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Searched refs:RISCV_IOMMU_DC_TC_V (Results 1 – 2 of 2) sorted by relevance

/qemu/hw/riscv/
H A Driscv-iommu.c899 ctx->tc = RISCV_IOMMU_DC_TC_V; in riscv_iommu_ctx_fetch()
986 if (!(ctx->tc & RISCV_IOMMU_DC_TC_V)) { in riscv_iommu_ctx_fetch()
1100 if (ctx->tc & RISCV_IOMMU_DC_TC_V && in riscv_iommu_ctx_inval_devid_procid()
1103 ctx->tc &= ~RISCV_IOMMU_DC_TC_V; in riscv_iommu_ctx_inval_devid_procid()
1112 if (ctx->tc & RISCV_IOMMU_DC_TC_V && in riscv_iommu_ctx_inval_devid()
1114 ctx->tc &= ~RISCV_IOMMU_DC_TC_V; in riscv_iommu_ctx_inval_devid()
1122 if (ctx->tc & RISCV_IOMMU_DC_TC_V) { in riscv_iommu_ctx_inval_all()
1123 ctx->tc &= ~RISCV_IOMMU_DC_TC_V; in riscv_iommu_ctx_inval_all()
1155 if (ctx && (ctx->tc & RISCV_IOMMU_DC_TC_V)) { in riscv_iommu_ctx()
H A Driscv-iommu-bits.h291 #define RISCV_IOMMU_DC_TC_V BIT_ULL(0) macro