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Searched refs:RISCV_IOMMU_CQCSR_CQMF (Results 1 – 2 of 2) sorted by relevance

/qemu/hw/riscv/
H A Driscv-iommu.c1649 !!(ctrl & (RISCV_IOMMU_CQCSR_CMD_ILL | RISCV_IOMMU_CQCSR_CQMF))) { in riscv_iommu_process_cq_tail()
1660 RISCV_IOMMU_CQCSR_CQMF, 0); in riscv_iommu_process_cq_tail()
1678 RISCV_IOMMU_CQCSR_CQMF, 0); in riscv_iommu_process_cq_tail()
1833 ctrl_clr = RISCV_IOMMU_CQCSR_BUSY | RISCV_IOMMU_CQCSR_CQMF | in riscv_iommu_process_cq_control()
1988 cqcsr & RISCV_IOMMU_CQCSR_CQMF)) { in riscv_iommu_update_ipsr()
2395 stl_le_p(&s->regs_wc[RISCV_IOMMU_REG_CQCSR], RISCV_IOMMU_CQCSR_CQMF | in riscv_iommu_realize()
H A Driscv-iommu-bits.h162 #define RISCV_IOMMU_CQCSR_CQMF RISCV_IOMMU_QUEUE_MEM_FAULT macro