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Searched refs:RISCV_IOMMU_CQCSR_CIE (Results 1 – 4 of 4) sorted by relevance

/qemu/tests/qtest/libqos/
H A Driscv-iommu.h47 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE macro
/qemu/tests/qtest/
H A Driscv-iommu-test.c66 g_assert_cmpuint(reg & RISCV_IOMMU_CQCSR_CIE, ==, 0); in test_reg_reset()
/qemu/hw/riscv/
H A Driscv-iommu-bits.h161 #define RISCV_IOMMU_CQCSR_CIE RISCV_IOMMU_QUEUE_INTR_ENABLE macro
H A Driscv-iommu.c1812 if (ctrl & RISCV_IOMMU_CQCSR_CIE) { in riscv_iommu_process_cq_tail()
1984 if (cqcsr & RISCV_IOMMU_CQCSR_CIE && in riscv_iommu_update_ipsr()
2478 reg_clr = RISCV_IOMMU_CQCSR_CQEN | RISCV_IOMMU_CQCSR_CIE | in riscv_iommu_reset()