RISCV_EXCP_STORE_AMO_ADDR_MIS (reference) in projects: qemu

Searched refs:RISCV_EXCP_STORE_AMO_ADDR_MIS (Results 1 – 3 of 3) sorted by relevance

/qemu/target/riscv/
H A D	cpu_bits.h	`708 RISCV_EXCP_STORE_AMO_ADDR_MIS = 0x6, enumerator`
H A D	cpu_helper.c	`1723 cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; in riscv_cpu_do_unaligned_access() 2205 case RISCV_EXCP_STORE_AMO_ADDR_MIS: in riscv_cpu_do_interrupt()`
H A D	csr.c	`1778 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) \| \`