Home
last modified time | relevance | path

Searched refs:RISCV_EXCP_INST_ADDR_MIS (Results 1 – 5 of 5) sorted by relevance

/qemu/target/riscv/
H A Dop_helper.c287 riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); in helper_sret()
367 riscv_raise_exception(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); in check_ret_from_m_mode()
H A Dcpu_bits.h702 RISCV_EXCP_INST_ADDR_MIS = 0x0, enumerator
H A Dcpu_helper.c1713 cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; in riscv_cpu_do_unaligned_access()
2230 case RISCV_EXCP_INST_ADDR_MIS: in riscv_cpu_do_interrupt()
H A Dtranslate.c265 generate_exception(ctx, RISCV_EXCP_INST_ADDR_MIS); in gen_exception_inst_addr_mis()
H A Dcsr.c1772 #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \