| /qemu/tcg/i386/ |
| H A D | tcg-target-con-str.h | 12 REGS('a', 1u << TCG_REG_EAX)
13 REGS('b', 1u << TCG_REG_EBX)
14 REGS('c', 1u << TCG_REG_ECX)
15 REGS('d', 1u << TCG_REG_EDX)
16 REGS('S', 1u << TCG_REG_ESI)
17 REGS('D', 1u << TCG_REG_EDI)
19 REGS('r', ALL_GENERAL_REGS)
20 REGS('x', ALL_VECTOR_REGS)
21 REGS('q', ALL_BYTEL_REGS) /* regs that can be used as a byte operand */
22 REGS('L', ALL_GENERAL_REGS & ~SOFTMMU_RESERVE_REGS) /* qemu_ld/st */
[all …]
|
| /qemu/tcg/arm/ |
| H A D | tcg-target-con-str.h | 11 REGS('e', ALL_GENERAL_REGS & 0x5555) /* even regs */
12 REGS('r', ALL_GENERAL_REGS)
13 REGS('q', ALL_QLDST_REGS)
14 REGS('Q', ALL_QLDST_REGS & 0x5555) /* even qldst */
15 REGS('w', ALL_VECTOR_REGS)
|
| /qemu/tcg/ppc/ |
| H A D | tcg-target-con-str.h | 11 REGS('r', ALL_GENERAL_REGS)
12 REGS('o', ALL_GENERAL_REGS & 0xAAAAAAAAu) /* odd registers */
13 REGS('v', ALL_VECTOR_REGS)
|
| /qemu/tcg/s390x/ |
| H A D | tcg-target-con-str.h | 11 REGS('r', ALL_GENERAL_REGS)
12 REGS('v', ALL_VECTOR_REGS)
13 REGS('o', 0xaaaa) /* odd numbered general regs */
|
| /qemu/target/hexagon/imported/ |
| H A D | shift.idef | 30 #define RSHIFTTYPES(TAGEND,REGD,REGS,REGSTYPE,ACC,ACCSRC,SAT,SATOPT,ATTRS) \
31 Q6INSN(S2_asr_r_##TAGEND,#REGD "32" #ACC "=asr(" #REGS "32,Rt32)" #SATOPT,ATTRIBS(ATTRS), \
35 REGD##V = SAT(ACCSRC ACC fBIDIR_ASHIFTR(REGS##V,shamt,REGSTYPE)); \
38 Q6INSN(S2_asl_r_##TAGEND,#REGD "32" #ACC "=asl(" #REGS "32,Rt32)" #SATOPT,ATTRIBS(ATTRS), \
42 REGD##V = SAT(ACCSRC ACC fBIDIR_ASHIFTL(REGS##V,shamt,REGSTYPE)); \
45 Q6INSN(S2_lsr_r_##TAGEND,#REGD "32" #ACC "=lsr(" #REGS "32,Rt32)" #SATOPT,ATTRIBS(ATTRS), \
49 REGD##V = SAT(ACCSRC ACC fBIDIR_LSHIFTR(REGS##V,shamt,REGSTYPE)); \
52 Q6INSN(S2_lsl_r_##TAGEND,#REGD "32" #ACC "=lsl(" #REGS "32,Rt32)" #SATOPT,ATTRIBS(ATTRS), \
56 REGD##V = SAT(ACCSRC ACC fBIDIR_LSHIFTL(REGS##V,shamt,REGSTYPE)); \
76 #define RSATSHIFTTYPES(TAGEND,REGD,REGS,REGSTYPE) \
[all …]
|
| /qemu/tcg/riscv/ |
| H A D | tcg-target-con-str.h | 11 REGS('r', ALL_GENERAL_REGS)
12 REGS('v', ALL_VECTOR_REGS)
|
| /qemu/tcg/loongarch64/ |
| H A D | tcg-target-con-str.h | 16 REGS('r', ALL_GENERAL_REGS)
17 REGS('w', ALL_VECTOR_REGS)
|
| /qemu/tcg/aarch64/ |
| H A D | tcg-target-con-str.h | 11 REGS('r', ALL_GENERAL_REGS)
12 REGS('w', ALL_VECTOR_REGS)
|
| /qemu/target/arm/ |
| H A D | cpregs.h | 1018 #define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ argument
1020 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
1021 define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \
1022 ARRAY_SIZE(REGS)); \
1025 #define define_arm_cp_regs(CPU, REGS) \ argument
1026 define_arm_cp_regs_with_opaque(CPU, REGS, NULL)
1054 #define modify_arm_cp_regs(REGS, MODS) \ argument
1056 QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) == 0); \
1058 modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \
|
| /qemu/tcg/tci/ |
| H A D | tcg-target-con-str.h | 11 REGS('r', MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS))
|
| /qemu/tcg/sparc64/ |
| H A D | tcg-target-con-str.h | 11 REGS('r', ALL_GENERAL_REGS)
|
| /qemu/tcg/mips/ |
| H A D | tcg-target-con-str.h | 11 REGS('r', ALL_GENERAL_REGS)
|
| /qemu/tcg/ |
| H A D | tcg.c | 3409 #define REGS(CASE, MASK) \ in process_constraint_sets() macro
3414 #undef REGS in process_constraint_sets()
|