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Searched refs:RB (Results 1 – 5 of 5) sorted by relevance

/qemu/disas/
H A Dalpha.c306 #define RB (RA + 1) macro
308 #define RC (RB + 1)
654 #define ARG_OPR { RA, RB, DRC1 }
656 #define ARG_OPRZ1 { ZA, RB, DRC1 }
803 { "mov", OPR(0x11,0x20), BASE, { ZA, RB, RC } }, /* pseudo */
1553 { "hw_mtpr", OP(0x1D), OP_MASK, EV6, { ZA, RB, EV6HWINDEX } },
/qemu/target/microblaze/
H A Dinsns.decode155 # Note that flt and fint, unlike fsqrt, are documented as having the RB
/qemu/tcg/ppc/
H A Dtcg-target.c.inc686 #define RB(r) ((r)<<11)
702 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
703 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
740 /* The low bit here is set if the RA and RB fields must be inverted. */
1229 load_insn |= VRT(ret) | RB(TCG_REG_TMP1);
1236 load_insn = LVX | VRT(ret) | RB(TCG_REG_TMP1);
1743 op |= const_arg2 ? arg2 & 0xffff : RB(arg2);
3901 tcg_out32(s, MTVSRDD | VRT(dst) | RA(src) | RB(src));
/qemu/hw/virtio/
H A Dtrace-events24 …4_t offset) "%d:%s: size:0x%"PRIx64" GPA:0x%"PRIx64" QVA/userspace:0x%"PRIx64" RB offset:0x%"PRIx64
/qemu/target/ppc/translate/
H A Dvmx-impl.c.inc402 * lvsl VRT,RA,RB - Load Vector for Shift Left
439 * lvsr VRT,RA,RB - Load Vector for Shift Right
1822 * RB is 0x12345678, executing "vinsw VRT,RB,14" results in