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Searched refs:RA (Results 1 – 10 of 10) sorted by relevance

/qemu/hw/net/
H A De1000x_common.c98 for (rp = mac + RA; rp < mac + RA + 32; rp += 2) { in e1000x_rx_group_filter()
105 trace_e1000x_rx_flt_ucast_match((int)(rp - mac - RA) / 2, in e1000x_rx_group_filter()
174 mac_regs[RA] = 0; in e1000x_reset_mac_addr()
175 mac_regs[RA + 1] = E1000_RAH_AV; in e1000x_reset_mac_addr()
177 mac_regs[RA] |= mac_addr[i] << (8 * i); in e1000x_reset_mac_addr()
178 mac_regs[RA + 1] |= in e1000x_reset_mac_addr()
H A De1000.c1065 if (index == RA + 1) { in mac_writereg()
1066 macaddr[0] = cpu_to_le32(s->mac_reg[RA]); in mac_writereg()
1067 macaddr[1] = cpu_to_le32(s->mac_reg[RA + 1]); in mac_writereg()
1169 [RA ... RA + 31] = &mac_readreg,
1201 [RA ... RA + 31] = &mac_writereg,
1544 VMSTATE_UINT32_SUB_ARRAY(mac_reg, E1000State, RA, 32),
H A De1000_common.h42 defreg(WUFC), defreg(RA), defreg(MTA), defreg(CRCERRS),
H A De1000e_core.c2720 macaddr[0] = cpu_to_le32(core->mac[RA]); in e1000e_mac_setmacaddr()
2721 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); in e1000e_mac_setmacaddr()
3067 [RA ... RA + 31] = e1000e_mac_readreg,
3149 e1000e_putreg(RA),
3214 [RA + 1] = e1000e_mac_setmacaddr,
3220 [RA + 2 ... RA + 31] = e1000e_mac_writereg,
H A Digb_common.h67 defreg(WUFC), defreg(RA), defreg(MTA), defreg(CRCERRS),
H A Digb_core.c1092 for (macp = core->mac + RA; macp < core->mac + RA + 32; macp += 2) { in igb_receive_assign()
3007 macaddr[0] = cpu_to_le32(core->mac[RA]); in igb_mac_setmacaddr()
3008 macaddr[1] = cpu_to_le32(core->mac[RA + 1]); in igb_mac_setmacaddr()
3614 [RA ... RA + 31] = igb_mac_readreg,
4027 [RA] = igb_mac_writereg,
4028 [RA + 1] = igb_mac_setmacaddr,
4029 [RA + 2 ... RA + 31] = igb_mac_writereg,
/qemu/disas/
H A Dalpha.c304 #define RA (UNUSED + 1) macro
306 #define RB (RA + 1)
648 #define ARG_BRA { RA, BDISP }
652 #define ARG_MEM { RA, MDISP, PRB }
654 #define ARG_OPR { RA, RB, DRC1 }
655 #define ARG_OPRL { RA, LIT, DRC1 }
659 #define ARG_EV4HWMEM { RA, EV4HWDISP, PRB }
660 #define ARG_EV4HWMPR { RA, RBA, EV4HWINDEX }
661 #define ARG_EV5HWMEM { RA, EV5HWDISP, PRB }
662 #define ARG_EV6HWMEM { RA, EV6HWDISP, PRB }
[all …]
/qemu/tcg/ppc/
H A Dtcg-target.c.inc685 #define RA(r) ((r)<<16)
702 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
703 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
704 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
705 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
740 /* The low bit here is set if the RA and RB fields must be inverted. */
870 | VRT(arg) | RA(ret));
879 | VRT(ret) | RA(arg));
904 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb | rc);
918 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh & 0x1f) | MB(mb) | ME(me) | rc);
[all …]
/qemu/target/ppc/translate/
H A Dfixedpoint-impl.c.inc1311 /* if RA=0, the instruction form is invalid */
H A Dvmx-impl.c.inc402 * lvsl VRT,RA,RB - Load Vector for Shift Left
439 * lvsr VRT,RA,RB - Load Vector for Shift Right