Home
last modified time | relevance | path

Searched refs:PRV_U (Results 1 – 9 of 9) sorted by relevance

/qemu/target/riscv/
H A Dop_helper.c303 mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); in helper_sret()
308 prev_priv == PRV_U; in helper_sret()
380 if (prev_priv == PRV_U || (prev_virt && in ssdbltrp_mxret()
381 (prev_priv == PRV_S || prev_priv == PRV_U))) { in ssdbltrp_mxret()
384 if (prev_virt && prev_priv == PRV_U) { in ssdbltrp_mxret()
406 riscv_has_ext(env, RVU) ? PRV_U : PRV_M); in helper_mret()
509 if (env->priv == PRV_U) { in helper_ctr_clear()
528 bool prv_u = env->priv == PRV_U; in helper_wfi()
546 if (env->virt_enabled && (env->priv == PRV_S || env->priv == PRV_U) && in helper_wrs_nto()
559 (env->priv == PRV_U || in helper_tlb_flush()
[all …]
H A Dcpu_helper.c77 case PRV_U: in cpu_get_fcfien()
104 case PRV_U: in cpu_get_bcfien()
164 case PRV_U: in riscv_pm_get_pmm()
189 if (priv_mode == PRV_U) { in riscv_pm_get_virt_pmm()
812 case PRV_U: in riscv_ctr_priv_to_mask()
829 case PRV_U: in riscv_ctr_get_control()
856 src_prv = PRV_U; in riscv_ctr_check_xte()
858 tgt_prv = PRV_U; in riscv_ctr_check_xte()
862 if (src_virt && src_prv == PRV_U) { in riscv_ctr_check_xte()
867 case PRV_U: in riscv_ctr_check_xte()
[all …]
H A Dpmu.c116 (env->priv == PRV_U && virt_on && in riscv_pmu_incr_ctr_rv32()
120 (env->priv == PRV_U && !virt_on && in riscv_pmu_incr_ctr_rv32()
157 (env->priv == PRV_U && virt_on && in riscv_pmu_incr_ctr_rv64()
161 (env->priv == PRV_U && !virt_on && in riscv_pmu_incr_ctr_rv64()
H A Dcpu_bits.h637 #define PRV_U 0 macro
H A Dcsr.c67 if (env->priv == PRV_U && !(env->sstateen[index] & bit)) { in smstateen_acc_ok()
72 if (env->priv == PRV_U && riscv_has_ext(env, RVS)) { in smstateen_acc_ok()
152 (env->priv == PRV_U && !get_field(env->scounteren, ctr_mask))) { in ctr()
157 if (riscv_has_ext(env, RVS) && env->priv == PRV_U && in ctr()
823 } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { in seed()
1278 curr_val += counter_arr[PRV_U]; in riscv_pmu_ctr_get_fixed_counters_val()
1286 curr_val += counter_arr_virt[PRV_U]; in riscv_pmu_ctr_get_fixed_counters_val()
1963 case PRV_U: in legalize_mpp()
H A Dcpu.h729 case PRV_U: in cpu_get_xl()
H A Dcpu.c764 env->priv = PRV_U; in riscv_cpu_reset_hold()
/qemu/target/riscv/insn_trans/
H A Dtrans_privileged.c.inc61 if (semihosting_enabled(ctx->priv == PRV_U) &&
H A Dtrans_xthead.c.inc272 if (ctx->priv == PRV_U) { \