1 /*
2 * QEMU Sun4u/Sun4v System Emulator
3 *
4 * Copyright (c) 2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/error-report.h"
28 #include "qapi/error.h"
29 #include "qemu/datadir.h"
30 #include "cpu.h"
31 #include "exec/target_page.h"
32 #include "hw/irq.h"
33 #include "hw/pci/pci.h"
34 #include "hw/pci/pci_bridge.h"
35 #include "hw/pci/pci_host.h"
36 #include "hw/qdev-properties.h"
37 #include "hw/pci-host/sabre.h"
38 #include "hw/char/serial-isa.h"
39 #include "hw/char/serial-mm.h"
40 #include "hw/char/parallel-isa.h"
41 #include "hw/rtc/m48t59.h"
42 #include "migration/vmstate.h"
43 #include "hw/input/i8042.h"
44 #include "hw/block/fdc.h"
45 #include "net/net.h"
46 #include "qemu/timer.h"
47 #include "system/runstate.h"
48 #include "system/system.h"
49 #include "hw/boards.h"
50 #include "hw/nvram/sun_nvram.h"
51 #include "hw/nvram/chrp_nvram.h"
52 #include "hw/sparc/sparc64.h"
53 #include "hw/nvram/fw_cfg.h"
54 #include "hw/sysbus.h"
55 #include "hw/ide/pci.h"
56 #include "hw/loader.h"
57 #include "hw/fw-path-provider.h"
58 #include "elf.h"
59 #include "trace.h"
60 #include "qom/object.h"
61
62 #define KERNEL_LOAD_ADDR 0x00404000
63 #define CMDLINE_ADDR 0x003ff000
64 #define PROM_SIZE_MAX (4 * MiB)
65 #define PROM_VADDR 0x000ffd00000ULL
66 #define PBM_SPECIAL_BASE 0x1fe00000000ULL
67 #define PBM_MEM_BASE 0x1ff00000000ULL
68 #define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL)
69 #define PROM_FILENAME "openbios-sparc64"
70 #define NVRAM_SIZE 0x2000
71 #define BIOS_CFG_IOPORT 0x510
72 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
73 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
74 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
75
76 #define IVEC_MAX 0x40
77
78 struct hwdef {
79 uint16_t machine_id;
80 uint64_t prom_addr;
81 uint64_t console_serial_base;
82 };
83
84 struct EbusState {
85 /*< private >*/
86 PCIDevice parent_obj;
87
88 ISABus *isa_bus;
89 qemu_irq *isa_irqs_in;
90 qemu_irq isa_irqs_out[ISA_NUM_IRQS];
91 uint64_t console_serial_base;
92 MemoryRegion bar0;
93 MemoryRegion bar1;
94 };
95
96 #define TYPE_EBUS "ebus"
OBJECT_DECLARE_SIMPLE_TYPE(EbusState,EBUS)97 OBJECT_DECLARE_SIMPLE_TYPE(EbusState, EBUS)
98
99 const char *fw_cfg_arch_key_name(uint16_t key)
100 {
101 static const struct {
102 uint16_t key;
103 const char *name;
104 } fw_cfg_arch_wellknown_keys[] = {
105 {FW_CFG_SPARC64_WIDTH, "width"},
106 {FW_CFG_SPARC64_HEIGHT, "height"},
107 {FW_CFG_SPARC64_DEPTH, "depth"},
108 };
109
110 for (size_t i = 0; i < ARRAY_SIZE(fw_cfg_arch_wellknown_keys); i++) {
111 if (fw_cfg_arch_wellknown_keys[i].key == key) {
112 return fw_cfg_arch_wellknown_keys[i].name;
113 }
114 }
115 return NULL;
116 }
117
fw_cfg_boot_set(void * opaque,const char * boot_device,Error ** errp)118 static void fw_cfg_boot_set(void *opaque, const char *boot_device,
119 Error **errp)
120 {
121 fw_cfg_modify_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
122 }
123
sun4u_NVRAM_set_params(Nvram * nvram,uint16_t NVRAM_size,const char * arch,ram_addr_t RAM_size,const char * boot_devices,uint32_t kernel_image,uint32_t kernel_size,const char * cmdline,uint32_t initrd_image,uint32_t initrd_size,uint32_t NVRAM_image,int width,int height,int depth,const uint8_t * macaddr)124 static int sun4u_NVRAM_set_params(Nvram *nvram, uint16_t NVRAM_size,
125 const char *arch, ram_addr_t RAM_size,
126 const char *boot_devices,
127 uint32_t kernel_image, uint32_t kernel_size,
128 const char *cmdline,
129 uint32_t initrd_image, uint32_t initrd_size,
130 uint32_t NVRAM_image,
131 int width, int height, int depth,
132 const uint8_t *macaddr)
133 {
134 unsigned int i;
135 int sysp_end;
136 uint8_t image[0x1ff0];
137 NvramClass *k = NVRAM_GET_CLASS(nvram);
138
139 memset(image, '\0', sizeof(image));
140
141 /* OpenBIOS nvram variables partition */
142 sysp_end = chrp_nvram_create_system_partition(image, 0, 0x1fd0);
143
144 /* Free space partition */
145 chrp_nvram_create_free_partition(&image[sysp_end], 0x1fd0 - sysp_end);
146
147 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
148
149 for (i = 0; i < sizeof(image); i++) {
150 (k->write)(nvram, i, image[i]);
151 }
152
153 return 0;
154 }
155
sun4u_load_kernel(const char * kernel_filename,const char * initrd_filename,ram_addr_t RAM_size,uint64_t * initrd_size,uint64_t * initrd_addr,uint64_t * kernel_addr,uint64_t * kernel_entry)156 static uint64_t sun4u_load_kernel(const char *kernel_filename,
157 const char *initrd_filename,
158 ram_addr_t RAM_size, uint64_t *initrd_size,
159 uint64_t *initrd_addr, uint64_t *kernel_addr,
160 uint64_t *kernel_entry)
161 {
162 int linux_boot;
163 unsigned int i;
164 long kernel_size;
165 uint8_t *ptr;
166 uint64_t kernel_top = 0;
167
168 linux_boot = (kernel_filename != NULL);
169
170 kernel_size = 0;
171 if (linux_boot) {
172 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, kernel_entry,
173 kernel_addr, &kernel_top, NULL,
174 ELFDATA2MSB, EM_SPARCV9, 0, 0);
175 if (kernel_size < 0) {
176 *kernel_addr = KERNEL_LOAD_ADDR;
177 *kernel_entry = KERNEL_LOAD_ADDR;
178 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
179 RAM_size - KERNEL_LOAD_ADDR, true,
180 TARGET_PAGE_SIZE);
181 }
182 if (kernel_size < 0) {
183 kernel_size = load_image_targphys(kernel_filename,
184 KERNEL_LOAD_ADDR,
185 RAM_size - KERNEL_LOAD_ADDR);
186 }
187 if (kernel_size < 0) {
188 error_report("could not load kernel '%s'", kernel_filename);
189 exit(1);
190 }
191 /* load initrd above kernel */
192 *initrd_size = 0;
193 if (initrd_filename && kernel_top) {
194 *initrd_addr = TARGET_PAGE_ALIGN(kernel_top);
195
196 *initrd_size = load_image_targphys(initrd_filename,
197 *initrd_addr,
198 RAM_size - *initrd_addr);
199 if ((int)*initrd_size < 0) {
200 error_report("could not load initial ram disk '%s'",
201 initrd_filename);
202 exit(1);
203 }
204 }
205 if (*initrd_size > 0) {
206 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
207 ptr = rom_ptr(*kernel_addr + i, 32);
208 if (ptr && ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
209 stl_p(ptr + 24, *initrd_addr + *kernel_addr);
210 stl_p(ptr + 28, *initrd_size);
211 break;
212 }
213 }
214 }
215 }
216 return kernel_size;
217 }
218
219 typedef struct ResetData {
220 SPARCCPU *cpu;
221 uint64_t prom_addr;
222 } ResetData;
223
224 #define TYPE_SUN4U_POWER "power"
225 OBJECT_DECLARE_SIMPLE_TYPE(PowerDevice, SUN4U_POWER)
226
227 struct PowerDevice {
228 SysBusDevice parent_obj;
229
230 MemoryRegion power_mmio;
231 };
232
233 /* Power */
power_mem_read(void * opaque,hwaddr addr,unsigned size)234 static uint64_t power_mem_read(void *opaque, hwaddr addr, unsigned size)
235 {
236 return 0;
237 }
238
power_mem_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)239 static void power_mem_write(void *opaque, hwaddr addr,
240 uint64_t val, unsigned size)
241 {
242 /* According to a real Ultra 5, bit 24 controls the power */
243 if (val & 0x1000000) {
244 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
245 }
246 }
247
248 static const MemoryRegionOps power_mem_ops = {
249 .read = power_mem_read,
250 .write = power_mem_write,
251 .endianness = DEVICE_BIG_ENDIAN,
252 .valid = {
253 .min_access_size = 4,
254 .max_access_size = 4,
255 },
256 };
257
power_realize(DeviceState * dev,Error ** errp)258 static void power_realize(DeviceState *dev, Error **errp)
259 {
260 PowerDevice *d = SUN4U_POWER(dev);
261 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
262
263 memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d,
264 "power", sizeof(uint32_t));
265
266 sysbus_init_mmio(sbd, &d->power_mmio);
267 }
268
power_class_init(ObjectClass * klass,const void * data)269 static void power_class_init(ObjectClass *klass, const void *data)
270 {
271 DeviceClass *dc = DEVICE_CLASS(klass);
272
273 dc->realize = power_realize;
274 }
275
276 static const TypeInfo power_info = {
277 .name = TYPE_SUN4U_POWER,
278 .parent = TYPE_SYS_BUS_DEVICE,
279 .instance_size = sizeof(PowerDevice),
280 .class_init = power_class_init,
281 };
282
ebus_isa_irq_handler(void * opaque,int n,int level)283 static void ebus_isa_irq_handler(void *opaque, int n, int level)
284 {
285 EbusState *s = EBUS(opaque);
286 qemu_irq irq = s->isa_irqs_out[n];
287
288 /* Pass ISA bus IRQs onto their gpio equivalent */
289 trace_ebus_isa_irq_handler(n, level);
290 if (irq) {
291 qemu_set_irq(irq, level);
292 }
293 }
294
295 /* EBUS (Eight bit bus) bridge */
ebus_realize(PCIDevice * pci_dev,Error ** errp)296 static void ebus_realize(PCIDevice *pci_dev, Error **errp)
297 {
298 EbusState *s = EBUS(pci_dev);
299 ISADevice *isa_dev;
300 SysBusDevice *sbd;
301 DeviceState *dev;
302 DriveInfo *fd[MAX_FD];
303 int i;
304
305 s->isa_bus = isa_bus_new(DEVICE(pci_dev), get_system_memory(),
306 pci_address_space_io(pci_dev), errp);
307 if (!s->isa_bus) {
308 error_setg(errp, "unable to instantiate EBUS ISA bus");
309 return;
310 }
311
312 /* ISA bus */
313 s->isa_irqs_in = qemu_allocate_irqs(ebus_isa_irq_handler, s, ISA_NUM_IRQS);
314 isa_bus_register_input_irqs(s->isa_bus, s->isa_irqs_in);
315 qdev_init_gpio_out_named(DEVICE(s), s->isa_irqs_out, "isa-irq",
316 ISA_NUM_IRQS);
317
318 /* Serial ports */
319 i = 0;
320 if (s->console_serial_base) {
321 serial_mm_init(pci_address_space(pci_dev), s->console_serial_base,
322 0, NULL, 115200, serial_hd(i), DEVICE_BIG_ENDIAN);
323 i++;
324 }
325 serial_hds_isa_init(s->isa_bus, i, MAX_ISA_SERIAL_PORTS);
326
327 /* Parallel ports */
328 parallel_hds_isa_init(s->isa_bus, MAX_PARALLEL_PORTS);
329
330 /* Keyboard */
331 isa_create_simple(s->isa_bus, TYPE_I8042);
332
333 /* Floppy */
334 for (i = 0; i < MAX_FD; i++) {
335 fd[i] = drive_get(IF_FLOPPY, 0, i);
336 }
337 isa_dev = isa_new(TYPE_ISA_FDC);
338 dev = DEVICE(isa_dev);
339 qdev_prop_set_uint32(dev, "dma", -1);
340 isa_realize_and_unref(isa_dev, s->isa_bus, &error_fatal);
341 isa_fdc_init_drives(isa_dev, fd);
342
343 /* Power */
344 dev = qdev_new(TYPE_SUN4U_POWER);
345 sbd = SYS_BUS_DEVICE(dev);
346 sysbus_realize_and_unref(sbd, &error_fatal);
347 memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240,
348 sysbus_mmio_get_region(sbd, 0));
349
350 /* PCI */
351 pci_dev->config[0x04] = 0x06; // command = bus master, pci mem
352 pci_dev->config[0x05] = 0x00;
353 pci_dev->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
354 pci_dev->config[0x07] = 0x03; // status = medium devsel
355 pci_dev->config[0x09] = 0x00; // programming i/f
356 pci_dev->config[0x0D] = 0x0a; // latency_timer
357
358 /*
359 * BAR0 is accessed by OpenBSD but not for ebus device access: allow any
360 * memory access to this region to succeed which allows the OpenBSD kernel
361 * to boot.
362 */
363 memory_region_init_io(&s->bar0, OBJECT(s), &unassigned_io_ops, s,
364 "bar0", 0x1000000);
365 pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0);
366 memory_region_init_alias(&s->bar1, OBJECT(s), "bar1",
367 pci_address_space_io(pci_dev), 0, 0x8000);
368 pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1);
369 }
370
371 static const Property ebus_properties[] = {
372 DEFINE_PROP_UINT64("console-serial-base", EbusState,
373 console_serial_base, 0),
374 };
375
ebus_class_init(ObjectClass * klass,const void * data)376 static void ebus_class_init(ObjectClass *klass, const void *data)
377 {
378 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
379 DeviceClass *dc = DEVICE_CLASS(klass);
380
381 k->realize = ebus_realize;
382 k->vendor_id = PCI_VENDOR_ID_SUN;
383 k->device_id = PCI_DEVICE_ID_SUN_EBUS;
384 k->revision = 0x01;
385 k->class_id = PCI_CLASS_BRIDGE_OTHER;
386 device_class_set_props(dc, ebus_properties);
387 }
388
389 static const TypeInfo ebus_info = {
390 .name = TYPE_EBUS,
391 .parent = TYPE_PCI_DEVICE,
392 .class_init = ebus_class_init,
393 .instance_size = sizeof(EbusState),
394 .interfaces = (const InterfaceInfo[]) {
395 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
396 { },
397 },
398 };
399
400 #define TYPE_OPENPROM "openprom"
401 typedef struct PROMState PROMState;
402 DECLARE_INSTANCE_CHECKER(PROMState, OPENPROM,
403 TYPE_OPENPROM)
404
405 struct PROMState {
406 SysBusDevice parent_obj;
407
408 MemoryRegion prom;
409 };
410
translate_prom_address(void * opaque,uint64_t addr)411 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
412 {
413 hwaddr *base_addr = (hwaddr *)opaque;
414 return addr + *base_addr - PROM_VADDR;
415 }
416
417 /* Boot PROM (OpenBIOS) */
prom_init(hwaddr addr,const char * bios_name)418 static void prom_init(hwaddr addr, const char *bios_name)
419 {
420 DeviceState *dev;
421 SysBusDevice *s;
422 char *filename;
423 int ret;
424
425 dev = qdev_new(TYPE_OPENPROM);
426 s = SYS_BUS_DEVICE(dev);
427 sysbus_realize_and_unref(s, &error_fatal);
428
429 sysbus_mmio_map(s, 0, addr);
430
431 /* load boot prom */
432 if (bios_name == NULL) {
433 bios_name = PROM_FILENAME;
434 }
435 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
436 if (filename) {
437 ret = load_elf(filename, NULL, translate_prom_address, &addr,
438 NULL, NULL, NULL, NULL, ELFDATA2MSB, EM_SPARCV9, 0, 0);
439 if (ret < 0 || ret > PROM_SIZE_MAX) {
440 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
441 }
442 g_free(filename);
443 } else {
444 ret = -1;
445 }
446 if (ret < 0 || ret > PROM_SIZE_MAX) {
447 error_report("could not load prom '%s'", bios_name);
448 exit(1);
449 }
450 }
451
prom_realize(DeviceState * ds,Error ** errp)452 static void prom_realize(DeviceState *ds, Error **errp)
453 {
454 PROMState *s = OPENPROM(ds);
455 SysBusDevice *dev = SYS_BUS_DEVICE(ds);
456
457 if (!memory_region_init_ram_nomigrate(&s->prom, OBJECT(ds), "sun4u.prom",
458 PROM_SIZE_MAX, errp)) {
459 return;
460 }
461
462 vmstate_register_ram_global(&s->prom);
463 memory_region_set_readonly(&s->prom, true);
464 sysbus_init_mmio(dev, &s->prom);
465 }
466
prom_class_init(ObjectClass * klass,const void * data)467 static void prom_class_init(ObjectClass *klass, const void *data)
468 {
469 DeviceClass *dc = DEVICE_CLASS(klass);
470
471 dc->realize = prom_realize;
472 }
473
474 static const TypeInfo prom_info = {
475 .name = TYPE_OPENPROM,
476 .parent = TYPE_SYS_BUS_DEVICE,
477 .instance_size = sizeof(PROMState),
478 .class_init = prom_class_init,
479 };
480
481
482 #define TYPE_SUN4U_MEMORY "memory"
483 typedef struct RamDevice RamDevice;
484 DECLARE_INSTANCE_CHECKER(RamDevice, SUN4U_RAM,
485 TYPE_SUN4U_MEMORY)
486
487 struct RamDevice {
488 SysBusDevice parent_obj;
489
490 MemoryRegion ram;
491 uint64_t size;
492 };
493
494 /* System RAM */
ram_realize(DeviceState * dev,Error ** errp)495 static void ram_realize(DeviceState *dev, Error **errp)
496 {
497 RamDevice *d = SUN4U_RAM(dev);
498 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
499
500 memory_region_init_ram_nomigrate(&d->ram, OBJECT(d), "sun4u.ram", d->size,
501 &error_fatal);
502 vmstate_register_ram_global(&d->ram);
503 sysbus_init_mmio(sbd, &d->ram);
504 }
505
ram_init(hwaddr addr,ram_addr_t RAM_size)506 static void ram_init(hwaddr addr, ram_addr_t RAM_size)
507 {
508 DeviceState *dev;
509 SysBusDevice *s;
510 RamDevice *d;
511
512 /* allocate RAM */
513 dev = qdev_new(TYPE_SUN4U_MEMORY);
514 s = SYS_BUS_DEVICE(dev);
515
516 d = SUN4U_RAM(dev);
517 d->size = RAM_size;
518 sysbus_realize_and_unref(s, &error_fatal);
519
520 sysbus_mmio_map(s, 0, addr);
521 }
522
523 static const Property ram_properties[] = {
524 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
525 };
526
ram_class_init(ObjectClass * klass,const void * data)527 static void ram_class_init(ObjectClass *klass, const void *data)
528 {
529 DeviceClass *dc = DEVICE_CLASS(klass);
530
531 dc->realize = ram_realize;
532 device_class_set_props(dc, ram_properties);
533 }
534
535 static const TypeInfo ram_info = {
536 .name = TYPE_SUN4U_MEMORY,
537 .parent = TYPE_SYS_BUS_DEVICE,
538 .instance_size = sizeof(RamDevice),
539 .class_init = ram_class_init,
540 };
541
sun4uv_init(MemoryRegion * address_space_mem,MachineState * machine,const struct hwdef * hwdef)542 static void sun4uv_init(MemoryRegion *address_space_mem,
543 MachineState *machine,
544 const struct hwdef *hwdef)
545 {
546 MachineClass *mc = MACHINE_GET_CLASS(machine);
547 SPARCCPU *cpu;
548 Nvram *nvram;
549 unsigned int i;
550 uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry;
551 SabreState *sabre;
552 PCIBus *pci_bus, *pci_busA, *pci_busB;
553 PCIDevice *ebus, *pci_dev;
554 SysBusDevice *s;
555 DeviceState *iommu, *dev;
556 FWCfgState *fw_cfg;
557 NICInfo *nd;
558 MACAddr macaddr;
559 bool onboard_nic;
560
561 /* init CPUs */
562 cpu = sparc64_cpu_devinit(machine->cpu_type, hwdef->prom_addr);
563
564 /* IOMMU */
565 iommu = qdev_new(TYPE_SUN4U_IOMMU);
566 sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu), &error_fatal);
567
568 /* set up devices */
569 ram_init(0, machine->ram_size);
570
571 prom_init(hwdef->prom_addr, machine->firmware);
572
573 /* Init sabre (PCI host bridge) */
574 sabre = SABRE(qdev_new(TYPE_SABRE));
575 qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE);
576 qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE);
577 object_property_set_link(OBJECT(sabre), "iommu", OBJECT(iommu),
578 &error_abort);
579 sysbus_realize_and_unref(SYS_BUS_DEVICE(sabre), &error_fatal);
580
581 /* sabre_config */
582 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 0, PBM_SPECIAL_BASE);
583 /* PCI configuration space */
584 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 1, PBM_SPECIAL_BASE + 0x1000000ULL);
585 /* pci_ioport */
586 sysbus_mmio_map(SYS_BUS_DEVICE(sabre), 2, PBM_SPECIAL_BASE + 0x2000000ULL);
587
588 /* Wire up PCI interrupts to CPU */
589 for (i = 0; i < IVEC_MAX; i++) {
590 qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i,
591 qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i));
592 }
593
594 pci_bus = PCI_HOST_BRIDGE(sabre)->bus;
595 pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA);
596 pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB);
597
598 /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is
599 reserved (leaving no slots free after on-board devices) however slots
600 0-3 are free on busB */
601 pci_bus_set_slot_reserved_mask(pci_bus, 0xfffffffc);
602 pci_bus_set_slot_reserved_mask(pci_busA, 0xfffffff1);
603 pci_bus_set_slot_reserved_mask(pci_busB, 0xfffffff0);
604
605 ebus = pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_EBUS);
606 qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
607 hwdef->console_serial_base);
608 pci_realize_and_unref(ebus, pci_busA, &error_fatal);
609
610 /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */
611 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7,
612 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ));
613 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6,
614 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ));
615 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1,
616 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ));
617 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12,
618 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ));
619 qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4,
620 qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ));
621
622 switch (vga_interface_type) {
623 case VGA_STD:
624 pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA");
625 vga_interface_created = true;
626 break;
627 case VGA_NONE:
628 break;
629 default:
630 abort(); /* Should not happen - types are checked in vl.c already */
631 }
632
633 memset(&macaddr, 0, sizeof(MACAddr));
634 onboard_nic = false;
635
636 nd = qemu_find_nic_info(mc->default_nic, true, NULL);
637 if (nd) {
638 pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), mc->default_nic);
639 dev = &pci_dev->qdev;
640 qdev_set_nic_properties(dev, nd);
641 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal);
642
643 memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
644 onboard_nic = true;
645 }
646 pci_init_nic_devices(pci_busB, mc->default_nic);
647
648 /* If we don't have an onboard NIC, grab a default MAC address so that
649 * we have a valid machine id */
650 if (!onboard_nic) {
651 qemu_macaddr_default_if_unset(&macaddr);
652 }
653
654 pci_dev = pci_new(PCI_DEVFN(3, 0), "cmd646-ide");
655 qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
656 pci_realize_and_unref(pci_dev, pci_busA, &error_fatal);
657 pci_ide_create_devs(pci_dev);
658
659 /* Map NVRAM into I/O (ebus) space */
660 dev = qdev_new("sysbus-m48t59");
661 qdev_prop_set_int32(dev, "base-year", 1968);
662 s = SYS_BUS_DEVICE(dev);
663 sysbus_realize_and_unref(s, &error_fatal);
664 memory_region_add_subregion(pci_address_space_io(ebus), 0x2000,
665 sysbus_mmio_get_region(s, 0));
666 nvram = NVRAM(dev);
667
668 initrd_size = 0;
669 initrd_addr = 0;
670 kernel_size = sun4u_load_kernel(machine->kernel_filename,
671 machine->initrd_filename,
672 machine->ram_size, &initrd_size, &initrd_addr,
673 &kernel_addr, &kernel_entry);
674
675 sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", machine->ram_size,
676 machine->boot_config.order,
677 kernel_addr, kernel_size,
678 machine->kernel_cmdline,
679 initrd_addr, initrd_size,
680 /* XXX: need an option to load a NVRAM image */
681 0,
682 graphic_width, graphic_height, graphic_depth,
683 (uint8_t *)&macaddr);
684
685 dev = qdev_new(TYPE_FW_CFG_IO);
686 qdev_prop_set_bit(dev, "dma_enabled", false);
687 object_property_add_child(OBJECT(ebus), TYPE_FW_CFG, OBJECT(dev));
688 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
689 memory_region_add_subregion(pci_address_space_io(ebus), BIOS_CFG_IOPORT,
690 &FW_CFG_IO(dev)->comb_iomem);
691
692 fw_cfg = FW_CFG(dev);
693 fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, (uint16_t)machine->smp.cpus);
694 fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)machine->smp.max_cpus);
695 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)machine->ram_size);
696 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
697 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_entry);
698 fw_cfg_add_i64(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
699 if (machine->kernel_cmdline) {
700 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
701 strlen(machine->kernel_cmdline) + 1);
702 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, machine->kernel_cmdline);
703 } else {
704 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
705 }
706 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
707 fw_cfg_add_i64(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
708 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, machine->boot_config.order[0]);
709
710 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
711 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
712 fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
713
714 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
715 }
716
717 enum {
718 sun4u_id = 0,
719 sun4v_id = 64,
720 };
721
722 /*
723 * Implementation of an interface to adjust firmware path
724 * for the bootindex property handling.
725 */
sun4u_fw_dev_path(FWPathProvider * p,BusState * bus,DeviceState * dev)726 static char *sun4u_fw_dev_path(FWPathProvider *p, BusState *bus,
727 DeviceState *dev)
728 {
729 PCIDevice *pci;
730
731 if (!strcmp(object_get_typename(OBJECT(dev)), "pbm-bridge")) {
732 pci = PCI_DEVICE(dev);
733
734 if (PCI_FUNC(pci->devfn)) {
735 return g_strdup_printf("pci@%x,%x", PCI_SLOT(pci->devfn),
736 PCI_FUNC(pci->devfn));
737 } else {
738 return g_strdup_printf("pci@%x", PCI_SLOT(pci->devfn));
739 }
740 }
741
742 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-hd")) {
743 return g_strdup("disk");
744 }
745
746 if (!strcmp(object_get_typename(OBJECT(dev)), "ide-cd")) {
747 return g_strdup("cdrom");
748 }
749
750 if (!strcmp(object_get_typename(OBJECT(dev)), "virtio-blk-device")) {
751 return g_strdup("disk");
752 }
753
754 return NULL;
755 }
756
757 static const struct hwdef hwdefs[] = {
758 /* Sun4u generic PC-like machine */
759 {
760 .machine_id = sun4u_id,
761 .prom_addr = 0x1fff0000000ULL,
762 .console_serial_base = 0,
763 },
764 /* Sun4v generic PC-like machine */
765 {
766 .machine_id = sun4v_id,
767 .prom_addr = 0x1fff0000000ULL,
768 .console_serial_base = 0,
769 },
770 };
771
772 /* Sun4u hardware initialisation */
sun4u_init(MachineState * machine)773 static void sun4u_init(MachineState *machine)
774 {
775 sun4uv_init(get_system_memory(), machine, &hwdefs[0]);
776 }
777
778 /* Sun4v hardware initialisation */
sun4v_init(MachineState * machine)779 static void sun4v_init(MachineState *machine)
780 {
781 sun4uv_init(get_system_memory(), machine, &hwdefs[1]);
782 }
783
784 static GlobalProperty hw_compat_sparc64[] = {
785 { "virtio-pci", "disable-legacy", "on", .optional = true },
786 { "virtio-device", "iommu_platform", "on" },
787 };
788 static const size_t hw_compat_sparc64_len = G_N_ELEMENTS(hw_compat_sparc64);
789
sun4u_class_init(ObjectClass * oc,const void * data)790 static void sun4u_class_init(ObjectClass *oc, const void *data)
791 {
792 MachineClass *mc = MACHINE_CLASS(oc);
793 FWPathProviderClass *fwc = FW_PATH_PROVIDER_CLASS(oc);
794
795 mc->desc = "Sun4u platform";
796 mc->init = sun4u_init;
797 mc->block_default_type = IF_IDE;
798 mc->max_cpus = 1; /* XXX for now */
799 mc->is_default = true;
800 mc->default_boot_order = "c";
801 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("TI-UltraSparc-IIi");
802 mc->ignore_boot_device_suffixes = true;
803 mc->default_display = "std";
804 mc->default_nic = "sunhme";
805 mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
806 fwc->get_dev_path = sun4u_fw_dev_path;
807 compat_props_add(mc->compat_props, hw_compat_sparc64, hw_compat_sparc64_len);
808 }
809
810 static const TypeInfo sun4u_type = {
811 .name = MACHINE_TYPE_NAME("sun4u"),
812 .parent = TYPE_MACHINE,
813 .class_init = sun4u_class_init,
814 .interfaces = (const InterfaceInfo[]) {
815 { TYPE_FW_PATH_PROVIDER },
816 { }
817 },
818 };
819
sun4v_class_init(ObjectClass * oc,const void * data)820 static void sun4v_class_init(ObjectClass *oc, const void *data)
821 {
822 MachineClass *mc = MACHINE_CLASS(oc);
823
824 mc->desc = "Sun4v platform";
825 mc->init = sun4v_init;
826 mc->block_default_type = IF_IDE;
827 mc->max_cpus = 1; /* XXX for now */
828 mc->default_boot_order = "c";
829 mc->default_cpu_type = SPARC_CPU_TYPE_NAME("Sun-UltraSparc-T1");
830 mc->default_display = "std";
831 mc->default_nic = "sunhme";
832 mc->no_parallel = !module_object_class_by_name(TYPE_ISA_PARALLEL);
833 }
834
835 static const TypeInfo sun4v_type = {
836 .name = MACHINE_TYPE_NAME("sun4v"),
837 .parent = TYPE_MACHINE,
838 .class_init = sun4v_class_init,
839 };
840
sun4u_register_types(void)841 static void sun4u_register_types(void)
842 {
843 type_register_static(&power_info);
844 type_register_static(&ebus_info);
845 type_register_static(&prom_info);
846 type_register_static(&ram_info);
847
848 type_register_static(&sun4u_type);
849 type_register_static(&sun4v_type);
850 }
851
852 type_init(sun4u_register_types)
853