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Searched refs:NR_IRQS (Results 1 – 6 of 6) sorted by relevance

/qemu/include/hw/intc/
H A Drx_icu.h42 NR_IRQS = 256 enumerator
51 struct IRQSource src[NR_IRQS];
57 uint8_t ir[NR_IRQS];
58 uint8_t dtcer[NR_IRQS];
59 uint8_t ier[NR_IRQS / 8];
/qemu/hw/intc/
H A Drx_icu.c96 if (n_IRQ >= NR_IRQS) { in rxicu_set_irq()
158 for (i = 0; i < NR_IRQS; i++) { in rxicu_ack_irq()
311 for (i = 0; i < NR_IRQS; i++) { in rxicu_realize()
330 qdev_init_gpio_in(DEVICE(d), rxicu_set_irq, NR_IRQS); in rxicu_init()
349 VMSTATE_UINT8_ARRAY(ir, RXICUState, NR_IRQS),
350 VMSTATE_UINT8_ARRAY(dtcer, RXICUState, NR_IRQS),
351 VMSTATE_UINT8_ARRAY(ier, RXICUState, NR_IRQS / 8),
/qemu/hw/sh4/
H A Dr2d.c69 NR_IRQS enumerator
97 IRQState irq[NR_IRQS];
101 static const struct { short irl; uint16_t msk; } irqtab[NR_IRQS] = {
120 for (i = 0; i < NR_IRQS; i++) { in update_irl()
202 qemu_init_irqs(s->irq, NR_IRQS, r2d_fpga_irq_set, s); in r2d_fpga_init()
/qemu/hw/rx/
H A Drx62n.c83 static const uint8_t ipr_table[NR_IRQS] = {
141 for (i = 0; i < NR_IRQS; i++) { in register_icu()
/qemu/target/openrisc/
H A Dcpu.h59 #define NR_IRQS 32 macro
H A Dcpu.c193 qdev_init_gpio_in_named(DEVICE(obj), openrisc_cpu_set_irq, "IRQ", NR_IRQS); in openrisc_cpu_initfn()