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Searched refs:MXL_RV64 (Results 1 – 13 of 13) sorted by relevance

/qemu/target/riscv/
H A Ddebug.c84 case MXL_RV64: in extract_trigger_type()
143 case MXL_RV64: in build_tdata1()
191 case MXL_RV64: in tdata1_validate()
240 case MXL_RV64: in textra_validate()
269 case MXL_RV64: in textra_validate()
384 case MXL_RV64: in trigger_textra_match()
424 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_breakpoint_size()
463 if (riscv_cpu_mxl(env) == MXL_RV64) { in type2_mcontrol_validate()
505 def_size = riscv_cpu_mxl(env) == MXL_RV64 ? 8 : 4; in type2_breakpoint_insert()
H A Dgdbstub.c68 case MXL_RV64: in riscv_cpu_gdb_read_register()
90 case MXL_RV64: in riscv_cpu_gdb_write_register()
92 if (env->xl < MXL_RV64) { in riscv_cpu_gdb_write_register()
369 case MXL_RV64: in riscv_cpu_register_gdb_regs_for_features()
H A Dtranslate.c131 #define get_xl(ctx) MXL_RV64
139 #define get_address_xl(ctx) MXL_RV64
352 case MXL_RV64: in get_gpr()
393 case MXL_RV64: in gen_set_gpr()
414 case MXL_RV64: in gen_set_gpri()
456 case MXL_RV64: in get_fpr_hs()
481 case MXL_RV64: in get_fpr_d()
503 case MXL_RV64: in dest_fpr()
526 case MXL_RV64: in gen_set_fpr_hs()
553 case MXL_RV64: in gen_set_fpr_d()
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H A Dcpu.c817 case MXL_RV64: in riscv_cpu_disas_set_info()
1179 case MXL_RV64: in riscv_cpu_validate_misa_mxl()
1966 case MXL_RV64: in prop_marchid_set()
2614 case MXL_RV64: in riscv_gdb_arch_name()
2929 .misa_mxl_max = MXL_RV64,
3009 .misa_mxl_max = MXL_RV64,
3013 .misa_mxl_max = MXL_RV64
3017 .misa_mxl_max = MXL_RV64,
3021 .misa_mxl_max = MXL_RV64,
3025 .misa_mxl_max = MXL_RV64,
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H A Dpmp.c597 riscv_cpu_mxl(env) == MXL_RV64 && in mseccfg_csr_write()
H A Dcsr.c745 if ((reg_index & 1) && (riscv_cpu_mxl(env) == MXL_RV64)) { in pmp()
917 case MXL_RV64: in read_vtype()
1895 case MXL_RV64: in add_status_sd()
2097 case MXL_RV64: in read_misa()
2098 misa = (target_ulong)MXL_RV64 << 62; in read_misa()
3185 if (riscv_cpu_mxl(env) == MXL_RV64) { in write_menvcfg()
3263 riscv_cpu_mxl(env) == MXL_RV64 && in write_senvcfg()
3324 if (riscv_cpu_mxl(env) == MXL_RV64) { in write_henvcfg()
4519 riscv_cpu_mxl(env) != MXL_RV64 || in write_hstatus()
H A Dcpu_bits.h588 MXL_RV64 = 2, enumerator
/qemu/target/riscv/insn_trans/
H A Dtrans_rvm.c.inc366 ctx->ol = MXL_RV64;
374 ctx->ol = MXL_RV64;
382 ctx->ol = MXL_RV64;
390 ctx->ol = MXL_RV64;
398 ctx->ol = MXL_RV64;
H A Dtrans_rvzicfiss.c.inc33 uint32_t tmp = (get_xl(ctx) == MXL_RV64) ? 8 : 4;
59 int tmp = (get_xl(ctx) == MXL_RV64) ? -8 : -4;
H A Dtrans_rvi.c.inc547 ctx->ol = MXL_RV64;
554 ctx->ol = MXL_RV64;
561 ctx->ol = MXL_RV64;
854 ctx->ol = MXL_RV64;
861 ctx->ol = MXL_RV64;
868 ctx->ol = MXL_RV64;
910 ctx->ol = MXL_RV64;
917 ctx->ol = MXL_RV64;
924 ctx->ol = MXL_RV64;
H A Dtrans_rvzacas.c.inc92 case MXL_RV64:
/qemu/target/riscv/tcg/
H A Dtcg-cpu.c1343 if (cpu->env.misa_mxl != MXL_RV64) { in cpu_set_profile()
/qemu/target/riscv/kvm/
H A Dkvm-cpu.c2107 .misa_mxl_max = MXL_RV64,